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P3

PPC464 core implementation

This course covers the IBM Power 464 core

Objectives

  • A boot firmware that initializes the MMU has been developped to explain the boot sequence.
  • Internal debug facilities are described.
  • The course focuses on PPC464 low level programming, especially the PowerPC EABI.
  • Examples of exception handlers are provided.
  • A DFT has been developed to explain how to use MAC instructions.
  • The Floating Point Unit operation is described.
  • The PLB ports as well as debug related signals are described to facilitate the hardware implementation.

  • This course has been delivered several times to engineers developing ASICs based on PPC464.
Labs are compiled with GNU compiler and run under Lauterbach Trace32 debugger.
A more detailed course description is available on request at training@ac6-training.com
  • Experience of a 32 bit processor or DSP is mandatory.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • Internal architecture overview
  • Highlighting instruction and data paths
  • Clocking
  • Programming model, the 4 register groups GPRs, SPRs, DCRs and memory mapped
  • CoreConnect-based SOCs
  • Pipeline basics
  • 7-stage pipeline operation
  • Speculative execution, guarded memory
  • Serialization
  • Cache basics
  • Cache programming interface
  • Process vs thread
  • Memory Management Unit
  • 36-bit real address space
  • Translation Lookaside Buffer initialisation
  • Cache control and debugging features
  • Load / store buffer, speculative loads, msync and mbar instructions
  • Booke E objectives
  • Branch instructions
  • Addressing modes
  • Load / store instructions
  • Semaphore management with lwarx / stwcx. Instructions
  • Arithmetical and logical instructions, shift and rotate instructions
  • Floating point unit, compliancy with IEEE754
  • Processing denormalized FP numbers
  • Floating point arithmetic instructions
  • FP-to-integer and integer-to-FP casting
  • The PowerPC EABI
  • Cache related instructions
  • 16-bit mac instructions to develop fixed point DSP algorithms
  • 2-cycle multiply option
  • Exception processing
  • Critical versus non critical interrupts
  • Syndrome registers updating when an exception is taken
  • Core timers : PIT, FIT and WDT
  • JTAG emulator use
  • The 464 instruction trace port
  • Real time trace when the PowerPC core executes cached instructions
  • Hardware vs software breakpoints
  • Signal naming convention
  • External connections
  • Clock and power management interface
  • CPU control interface
  • Reset interface
  • External interrupt controller interface
  • Instruction-side PLB interface
  • Data-side PLB interface
  • DCR interface
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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