PCI 3.0 Training | Ac6 Training

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IC1PCI 3.0
This course covers PCI bus version 3.0

Objectives

  • The training has been designed from the PCI3.0 specification.
  • It describes the read prefetch / write posting mechanisms and synchronization rules.
  • Transfer protocol is explained with the assistance of the Lecroy analyzer board.
  • The course emphasizes the host bridge operation especially the management of PCI accesses targetting cache enabled regions.
  • A software routine has been developped to show how to access the configuration space.
  • Also interrupt requests allocation, memory regions allocation are detailed in single PCI system and multiple PCI systems (PCI-to-PCI bridge).
  • The course explains how to tune the PCI performance: selecting optimized LT value, appropriate master priority, enabling fast-back-to-back.
A more detailed course description is available on request at training@ac6-training.com
    • Experience of a digital bus is mandatory
    • Experience of a 32-bit processor is recommended
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by quizzes at the end of sections.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • PCI specifications history
  • PCI bus features
  • PCI device types
  • Technological introduction
  • Architecture of recent PCs
  • Information buffering
  • Buffer management
  • Prefetchable vs non-prefetchable memory ranges
  • Synchronization rules
  • Producer / consumer model
  • Optional processings
  • PCI bus limitations
  • Transfer basics
  • Pinout, signal classes
  • Arbitration
  • Data transfer protocol
  • Address decoding in IO, MEM and CFG spaces
  • 64-bit data transfer
  • 64-bit addressing
  • Master initiated terminations
  • Target initiated terminations
  • Fast back-to-back
  • Parity control
  • Shared resource management
  • Bus analyse, benefit of a bus analyser / exerciser
  • PCI interrupts
  • Interrupt acknowledge transaction
  • Interrupt sharing
  • Message Signaled Interrupts
  • MSI-X
  • Reset, operating states
  • Cache basics
  • Snooping basics
  • Cacheability of RAM accessed by the host CPU through PCI
  • PCI masters accessing the host memory
  • PCI agent processor accessing the host memory
  • Switched wave switching vs Incident wave switching
  • Static specification
  • Dynamic specification : 33 MHz and 66 MHz
  • Clocking
  • Decoupling
  • Routing and layout recommendations
  • Compliance checklists
  • Configuration space mappings
  • Register description
  • PCI MEM and PCI IO mappings building
  • Expansion ROM
  • Capability list
  • Configuration transactions, IDSEL routing
  • Local vs distant CFG transaction
  • Generation of config transactions
  • Bus numbering
  • Address decode, transaction forwarding rules
  • Distant configuration cycles
  • Error management
  • Bus power state machine
  • PCI function power state machine
  • Programming interface
  • Passive bus PICMG PC
  • CMC/PMC mezzanine boards, BUSMODE pins management
  • CompactPCI introduction
  • PC104+ introduction
  • PC.MIP introduction
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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