RapidIO 3.0 Training | Ac6 Training

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IC5RapidIO 3.0
This course covers the RapidIO interconnect version 3.0

Objectives

  • Packet switching benefits compared to shared busses are highlighted.
  • The course explains the various traffic types that RapidIO supports: Input / output, Message and GSM.
  • Mechanisms like error recovery and flow control are explained through various sequences.
  • The course covers all features present in the RapidIO 3.0 specification, such as end-to-end flow control, multicast programming, data streaming and virtual output queuing extensions.
  • CC-NUMA cache coherency mechanism is studied.
  • The course describes the discovery sequence required to initialize the switches.
  • Details of RapidIO interfaces present in NXP and IDT devices are provided to explain how theoretical statements are actually implemented .
A more detailed course description is available on request at training@ac6-training.com
  • Experience of a digital bus such as PCI or Ethernet.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by quizzes at the end of sections.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • Limitations of parallel shared buses
  • Benefits of differential transmission
  • Gigabit Serdes
  • Layer model, features of logical, transport and physical layers
  • Packet encapsulation
  • Purpose of control symbols
  • Technical features: distributed memory vs message passing
  • Accessing memory mapped address ranges
  • Accessing the configuration space
  • Atomic transactions
  • Maintenance transaction
  • Port write operation
  • Message vs doorbell
  • Transmission of interrupts through doorbells, concept of virtual wires
  • Management of messages split into several packets
  • Detail of message passing implementation in NXP QorIQ devices
  • Snooping basics
  • GSM transactions, coherence domains
  • The CC-NUMA approach
  • Description of a directory entry: the sharing mask
  • Analysis of various cache coherency sequences
  • Mechanism of transporting an arbitrary protocol over a standard RAPIDIO interface
  • Traffic streams
  • Encapsulation methodology
  • Support for PDU of 64 kB through segmentation and reassembly
  • Class of services and virtual queues
  • Controlled flow list
  • Watermarks setting
  • XON-XOFF controls on transaction request flows
  • Physical layer requirements
  • Ordering rules
  • Packet routing through the network based on destination ID
  • Programming interface to read / write the routing tables
  • Multicast extensions
  • Multicast mask and multicast group
  • System exploration and initialization
  • System enumeration API
  • Hardware abstraction layer
  • Packet acknowledgement
  • Control symbols vs packet
  • Multicast event
  • Early processing of packets
  • Study of various sequences explaining the ability of RAPIDIO to recover from errors automatically by hardware
  • Port behaviour when error rate failed threshold is reached
  • Drop packet enable
  • Hot Swap Extensions
  • Port behaviour when error rate failed threshold is reached
  • Drop packet enable
  • System software notification of errors
  • Mapping flowID into 2-bit priority
  • Receiver based flow control, retry mechanism
  • Transmitter based flow control, management of transmit credits
  • Deadlock prevention
  • Features or sublayers PCS and PMA
  • Format of packets and symbols
  • Single VC mode vs multiple VC mode, purpose of VC status control symbol
  • The 8b/10b encoder / decoder
  • Special characters, comma detection
  • Lane synchronization
  • 1.25Gbaud, 2.5Gbaud, and 3.125Gbaud LP-Serial Links
  • 5Gbaud and 6.25Gbaud LP-Serial Links
  • Transmit emphasis tuning
  • Use of eye diagram to specify the electrical interface
  • 64B/67B PCS and PMA Layers
  • Scrambling
  • Ordered sequences
  • Electrical Specification for 10.3125 Gbaud LP-Serial Links
  • Adaptive Equalization
  • Head Of Line blocking
  • Congestion message
  • Traffic staging
  • Relationship with VC
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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