KEYSTONE II IMPLEMENTATION Training | Ac6 Training

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TK1KEYSTONE II IMPLEMENTATION
This course covers all SoCs belonging to the KeyStone II, AM5K2E, 66AK2H and 66AK2E

OBJECTIVES

  • The course details the hardware implementation of the Key Stone II.
  • The course focuses on the boot sequence, the clocking and the power management strategies.
  • The course explains all parameters that affect the performance of the system in order to easily perform the final tuning.
  • The Ethernet MACs, as well as the Queue Manager and the Network Coprocessor are detailed.
  • Interrupt management through ARM GIC is explained through a lab.
  • The course also covers the hardware implementation, particularly the power supplies and the clocking
  • All operation modes of EDMA3 are studied through use cases.
  • General purpose high speed interfaces PCIe and USB3.0 are also handled.

A more detailed course description is available on request at training@ac6-training.com
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by quizzes at the end of sections.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • Describing the architectures of AM5K2E, 66AK2H, 66AK2E SoCs
  • On-chip memories
  • Clarifying the internal data paths: TeraNet masters and slaves
  • Memory Protection Unit
  • Organization of a board based on Key Stone II
  • Summary of all peripheral features
  • Memory mapping
  • Cortex-A15 and integrated L2 cache instantiation options
  • Integrated interrupt controller (GIC), detail of interrupt mapping
  • Hardware big/little endian conversion
  • Local Power and Sleep Controller
  • Debug architecture
  • Introduction to CoreSight, DAP features
  • System Secure Controller SJC
  • Embedded Trace Macrocell
  • Power supplies, smart reflex
  • Clock Control Module
  • Reset Controller
  • General Purpose Input/Output pins
  • SerDes
  • DMA/QDMA Channel Logic
  • Transfer controller, types of transfers
  • Event queues
  • Transfer Request Submission Logic
  • Channel priority definition
  • DMA/QDMA Channel Logic
  • Parameter RAM (PaRAM):
  • • Linking transfers
  • • Channel controller shadow regions
  • DDR3 Controller
  • EMIF16
  • Configuration as Agent or Root Complex
  • Interrupt management, MSI
  • Error management
  • Configurable BAR filtering
  • Inbound and outbound window programming
  • Power management
  • Enhanced CSPI
  • I2C interfaces
  • UART
  • USB 3.0
  • 1G/10G Ethernet Controller
  • Ethernet switch
  • Multicore Navigator
  • Network coprocessor
Duration
4 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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