| M7 | 440SPe implementation |
This course covers AMCC 440SPe processor
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Objectives
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- Experience of a 32 bit processor or DSP is mandatory.
- Knowledge of PCI-X bus is recommended, see our course reference IC3 - PCI-X 2.0 course.
- Knowledge of PCI Express bus is recommended, see our course reference IC4 - PCI Express 3.0 course.
- Knowledge of Gigabit Ethernet is recommended, see our course reference N1 - Ethernet and switching course.
- Theoretical course
- PDF course material (in English) supplemented by a printed version for face-to-face courses.
- Online courses are dispensed using the Teams video-conferencing system.
- The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
- At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- Block diagram
- Internal bus organization : dual PLB, OPB, DCR
- Internal concurrent transfers examples
- Introduction to Integrated peripherals
- Hardware implementation
- 440SPe memory mapping
- Programming model
- Introduction to CoreConnect
- 2-way PLB crossbar, programming
- Bus errors recovery from syndrome registers
- PLB performance monitor
- Pipeline
- Internal caches
- Speculative loads, storage ordering and synchronization : msync & mbar instructions
- MMU
- Programming model
- Branch instructions
- Addressing modes, load & store instructions
- Integer instructions
- 16-bit mac instructions to develop DSP algorithms
- Exception management
- Exception priorities
- Core timers
- PowerPC EABI
- JTAG debug
- Real time trace
- Clocks synthesizer
- PCI-X clocking
- PCI Express clocking
- Clock and power management
- Low power modes
- Reset signals
- Initialization software requirements
- IIC bootstrap controller : processor configuration through the IIC port
- PCI-X bootstrap configuration
- Peripheral software reset
- Booting from local ROM in Host bridge mode
- Booting from local ROM in Agent bridge mode
- Booting from PCI
- L2 cache features
- Data movement between memory, L2 and L1 caches
- L2 cache programming
- SRAM controller
- Interrupt masking and acknowledgement sequences
- Critical interrupt handlers using vectorization
- Interrupts priority management
- General Purpose Timers
- DDR-SDRAM operation
- Jedec specification basics
- Hardware interface, SSTL-2 termination logic
- Differences between DDR-I and DDR-II
- ECC error correction
- Introduction to the 440SPe DDR-SDRAM controller
- Page management unit
- Initialization sequence
- Hardware implementation
- External bus pinout, driver enables
- Dynamic bus sizing
- Timing parameters
- Device-paced transfers
- DDR PCI-X operation
- Host vs agent configuration
- Data flows : Read prefetch and write posting buffers
- Inbound transactions handling, Outbound transactions handling
- Error handling
- Arbitration algorithm
- Boot modes, initialization / Reset sequence
- Sleep mode entering
- PCI-Express to PCI-X bridging
- Message passing
- Interrupts and MSI
- 8-lane host interface
- 4-lane secondary interfaces
- Root complex vs EndPoint configuration
- PCI Express functional cores
- Hardware implementation
- Power management
- Error handling
- Messaging
- 802.3 specification fundamentals : PHY and MAC layers
- 440SPE Ethernet controller organization
- PHY
- Flow control
- VLAN support
- Frame filtering
- Hash table usage in switch applications
- Memory Access Layer controller, buffer management
- Buffer descriptors initialization
- Errors management
- Parity generation and check functions
- Command block list
- DMA capability
- Message vs doorbell
- Management of inbound messages
- Management of outbound messages
- DMA operation
- GPIO
- GPIO interface signals
- Pin configuration
- UART
- FIFO mode
- Flow control signals management
- IIC
- IIC protocol fundamentals
- Transmission and reception sequence
- Serial boot ROM
Duration
5 days
Cost
2100 € HT
Calendar
To book a training session or for more information, please contact us on info@ac6-training.com.
Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.
You can also fill and send us the
registration form
This course can be provided either remotely, in our Paris training center or, worldwide, on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 2 working days before the course start (1 week for face-to-face courses).
Booking one of our trainings is subject to our
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