| FF1 | MCF5x07 implementation |
This course covers MCF5307 and MCF5407 ColdFire MCUs
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Objectives
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- Experience of a 32 bit processor or DSP is mandatory.
- Theoretical course
- PDF course material (in English) supplemented by a printed version for face-to-face courses.
- Online courses are dispensed using the Teams video-conferencing system.
- The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
- At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- Coldfire roadmap
- Differences between ColdFires and 68K processors
- 5307 block diagram
- Pinout
- Memory mapped I/O organization
- 5307 pipeline
- Programming model
- Addressing modes
- Instruction set
- Stack management, subroutine call and return
- C to assembly interface
- Exception management
- Internal SRAM
- 5307 cache operation
- Intrusive vs non-intrusive debug
- BDM port
- Hardware breakpoints
- Trace port
- Dynamic bus sizing
- Address decoding
- Arbitration
- Burst cycles
- Bus error management
- The interrupt controller
- The software watchdog
- Reset, self-configuration
- Clock synthesis
- General Purpose I/O pins
- SRAM connection, chip-select programming
- DRAM / SDRAM basics
- The 5x07 (S)DRAM controller : address decoding, refresh rate definition, address multiplexing selection
- Asynchronous ports
- Transmit and receive sequences
- Synchronous port : I2C basics
- Transmit and receive sequences
- Single address vs dual address transfers
- Hardware interface, hardware initiated transfers
- Programming model
- Capture mode
- Period selection
- Interrupt control
- V4 core enhancements
- Instruction set additions
- Enhanced memories
- On-chip DMA and serial ports modifications
Duration
4 days
Cost
1950 € HT
Calendar
To book a training session or for more information, please contact us on info@ac6-training.com.
Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.
You can also fill and send us the
registration form
This course can be provided either remotely, in our Paris training center or, worldwide, on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 2 working days before the course start (1 week for face-to-face courses).
Booking one of our trainings is subject to our
General Terms of Sales
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