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LLI

This course covers the Low Latency Interface (LLI) MIPI bus<p>

Objectives

  • The course starts with an overview of MIPI specification.
  • The chapters are studied with a bottom-top approach, starting with M-PHY and ending with LLI.
  • The electrical characteristics and related tests of the M-PHY layer are described.
  • The course explains the M-PHY state machines and clarifies the configuration of M-PHY through attributes.
  • LLI bridge from local interconnect to external M-PHY differential pairs is detailed.
  • All layers of LLI from Physical Adapter to Transaction are explained through Service Access Points and Primitives.
  • Companies interested in attending this course must adhere to MIPI organization.
  • This course has been designed for engineers in charge of SoC architecture, functional verification or silicon validation.

A more detailed course description is available on request at training@ac6-training.com
  • Basic knowledge on digital electronics.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • Termination scheme
  • Signaling schemes
  • Pulse Width Modulation
  • M-PHY type I modules
  • Embedding clock into the bitstream, 8b10b coding
  • Control symbols
  • PHY state definition
  • Transitions between states
  • HS-MODE BURST Operation
  • Configuration attributes
  • Test modes
  • Electrical characteristics, eye-diagrams
  • Recommended test functionality
  • Optical Media Converter
  • Services to transfer descriptor and configuration data between devices on a MIPI Interconnect
  • Underlying interconnect requirements
  • Accessing DDB Services through DDB Service Access Points
  • DDB-PDU format
  • DDB protocol support for Level 1 and Level 2 services
  • Objectives: accessing an external device exactly like a local IP, using memory-mapped transactions
  • Power management, Automatic Save State
  • M-PHY Adapter layer
  • Data link layer, independent flow control using Traffic Classes
  • Transaction layer, configuration space, ordering rules
  • Device enumeration
Duration
2 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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