IC8
VPX and Open VPX
This course covers the VPX and Open VPX VITA standards
Objectives
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- Basic knowledge of high-speed serial interconnect is recommended, such as PCIe, SRIO or Gigabit/10G Ethernet.
- See our courses on PCI Express reference IC4 - PCI Express 3.0 course, RapidIO reference IC5 - RapidIO 3.0 course, Gigabit Ethernet, reference N1 - Ethernet and switching course and 10 Gigabit Ethernet, reference N3 - Ethernet 10 Gigabit course
- Theoretical course
- PDF material in English (printed for face-to-face); online over Teams.
- Trainer assistance throughout.
- Each session starts with a trainee check-in.
- Any embedded systems engineer or technician with the above prerequisites.
- Prerequisites are checked before the course starts, against the prerequisites published on this page.
- Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
- At the end of the course, each participant receives a training completion certificate.
Course Outline
- Objectives of this standard
- Limitations of shared bus system
- Implementation of a switch fabric
- Evolutionary roadmap for VME users
- Overview, definitions
- System signals
- Power supply
- System controller
- Board form factor
- Connector pin definitions, P0 utility connector
- Alignment and keying
- Electrical budgets for protocol standards
- Power wafer current ratings
- Connector pin definitions, P1
- 3U modules, P2 connector, differential vs single-ended pinout
- 6U modules, P2-P6 connectors
- Backplane
- Power delivery
- Backplane fabric connections electrical requirements
- System management signals connection
- Hybrid backplane
- Example: five slot fabric full mesh backplane routing
- VME bus signals mapping on VPX
- SYSRESET management
- P3-P6 connector pin mappings
- Serial RapidIO on VPX fabric connector
- Assigning Serial RapidIO ports to the VPX P1/J1 connector
- PCI Express on VPX fabric connector
- Reference clock
- System reset
- Assigning PCIe ports to the VPX P1/J1 connector
- Gigabit Ethernet control plane on VPX fabric connector
- 1000BASE-BX or 1000BASE-KX interface on each of the Ultra-Thin Pipe ports
- Gigabit Ethernet on VPX fabric connector
- Pipe definition, Ethernet Fat Pipe 10GBASE-KX4, 10GBASE-BX4, Ultra Thin Pipe 1000BASE-KX, 1000BASE-BX
- Mezzanine card Rear I/O pattern maps
- Mezzanine Type label
- 3U vita 46.0 connector pin mapping
- 6U vita 46.0 connector pin mapping
- Electrical specifications
- General arrangement of front and read modules
- Alignment keying sockets
- Current and power per RTM slot
- Connector pin definitions RP0
- Bringing versatile system architectural solutions to the VPX market
- Description of a series of standard profiles
- System Interoperability Diagram with interface content
- Profiles definition
- Backplane profile topologies: centralized, distributed, hybrid
- Mechanical requirements
- Slot profile
- Backplane profile
- Module profile
- Standard development chassis profile
More
To book a training session or for more information, please contact us on info@ac6-training.com.
Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.
You can also fill and send us the registration form
This course can be provided either remotely, in our Paris training center or worldwide on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.
Last update of course schedule: 27 June 2026
Booking one of our trainings is subject to our General Terms of Sales
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