| FD1 | DSP568XX implementation |
This course covers the 568XX 16-bit DSP NXP family
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Objectives
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- Basic knowledge about signal processing and motor control.
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Knowledge of CAN bus is recommended, see our course reference CAN bus, reference IA1 - CAN bus course
- Theoretical course
- PDF course material (in English) supplemented by a printed version for face-to-face courses.
- Online courses are dispensed using the Teams video-conferencing system.
- The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
- At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- Arithmetic processing of real-time signals
- Filtering, convolution, correlation
- Modified dual Harvard architecture
- DSP 568XX family introduction, compatibility with 5600X DSPs
- Introduction of motor types
- Core buses
- Processing states
- Reset, low voltage, stop and wait operations
- 56807 mapping
- The Data ALU
- The Address Generation Unit
- The Program Control Unit
- The instruction set
- C-to-assembly interface
- Software techniques
- Exception management
- The interrupt routing performed by the ICTN
- The debugging support
- JTAG use to access the OnCE
- The embedded flash memory
- Program sequence
- Erase sequence
- On chip clock synthesis
- Wait state X data memory
- Wait state program memory
- Timer module pinout
- Operating modes
- OFLAG output signal
- Timing, pipelining
- Conversion sequence definition
- Synchronization to the PWM
- Optional sample correction
- Quadrature decoders pinout
- Configurable digital filters
- Watchdog timer implementation
- Independent or complementary channel operation
- Deadtime generators
- IFault protection
- SCI block diagram, IO signals
- Asynchronous vs synchronous operation modes
- Baud rate selection
- Bootstrap loading from the SCI
- Asynchronous transmit and receive sequences
- SPI synchronous communications basics
- Master vs slave selection
- Polarity selection
- The MSCAN controllers
- Message buffers structure
- ID bit masking
- Arbitration
- Timing and synchronization
- Error management
Duration
3 days
Cost
1650 € HT
Calendar
To book a training session or for more information, please contact us on info@ac6-training.com.
Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.
You can also fill and send us the
registration form
This course can be provided either remotely, in our Paris training center or, worldwide, on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 2 working days before the course start (1 week for face-to-face courses).
Booking one of our trainings is subject to our
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