Microchip SmartFusion2 Programming Training | Ac6 Training

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MSPMicrochip SmartFusion2 Programming
This course describe the Microcontroller Subsystem (MSS) of SmartFusion2 Microchip FPGAs

Objective

  • Get an Overview on the Cortex-M Architecture
  • Understand the Cortex-M Software implementation and debug
  • The Microchip Implementation and Embedded Development Kit (EDK) with Libero SoC and software Integrated Development environment (IDE) tools are described to create a hardware platform and the software to execute to programme it
  • Describe SmartFusion MSS Architecture, I/Os and understand the SmartFusion2 FPGA Fabric Interface
  • Become familiar with the MSS Peripherals
  • Basic knowledge of processor and FPGA technology
  • Knowledge of VHDL and C languages
  • Microchip LiberoSoC v12.0 and SoftConsole v6.0
  • SmartFusion2 based board
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by the trainer through the practical exercises, and by quizzes for sections without exercises.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • Microchip FPGA & SoC overview
  • Libero SoC overview
  • Create and Design
  • Constraint management
  • TestBench and Simulations
  • Programme and Debug
  • Microchip (Microsemi) tool’s
Exercise:  Creating a Libero Project for Firmware
Exercise:  Libero Project and SoftConsole
  • V7-M Architecture Overview
  • Core Architecture
    • Harvard Architecture, I-Code, D-Code and System Bus
    • Write Buffer
    • Registers (Two stack pointers)
    • States
    • Different Running-mode and Privileged Levels
    • System Control Block
    • Systick Timer
    • MPU Overview
  • Programming
    • Alignment and Endianness
    • CMSIS Library
  • Exception/ Interrupts Mechanism Overview
    • Vector Table
    • Interrupt entry and return Overview
    • Tail-Chaining
    • Pre-emption (Nesting)
    • NVIC Integrated Interrupt Controller
    • Exception Priority Management
    • Fault escalation
    • Debug Interface
  • System Level Interface
  • Integrated Configurable Debug
  • Cortex-M3 Processor Core Peripherals
    • Nested Vectored Interrupt Controller
    • System Control Block
    • System Timer
    • Memory Protection Unit
  • Cortex-M3 Processor Description
    • Programmers Model
    • Memory Model
    • Exception Model
    • Fault Handling
    • Power Management
  • Cortex-M3 Processor Instruction Set
    • CMSIS Functions
    • Memory Access Instructions
    • General Data Processing Instructions
    • Saturating Instructions
    • Branch and Control Instructions
  • Cortex-M3 Processor Peripherals
    • System Control Block
    • System Timer (Systick)
    • Memory Protection Unit
Exercise:  Cortex-M3 Mode Privilege
Exercise:  Cortex-M3 Exception Management
Exercise:  Cortex-M3 MPU
Exercise:  Cortex-M3 Real-Time Operating System (FreeRTOS)
  • Cache Matrix
  • Memory Mapping
  • Memory Maps and Transaction Mapping
  • Cache Locked Mode
  • How to use cache Controller
Exercise:  Cache Controller Configuration
  • Functional Description
  • Security
  • How to use eNVM
  • SYSREG Control Registers
  • DMA Controller Initialization
  • DMA Controller Operations
  • How to use HPDMA
  • HDMA Controller Register Map
  • Peripheral DMA Architecture Overview
  • How to use PDMA
  • PDMA Register Map
  • Architecture Overview
  • Functional Description
  • AHB-Lite Options
  • Implementation Considerations
  • How to Use FIC
  • Power-On Reset Generation Sequence
  • Power-Up to functional Time Data
  • CoreResetP Soft Reset Controller
    • Reset Topology
    • Implementation
  • How to use the Reset Controller
  • Centralized address decoding
  • Address gating logic
  • Address pipelining
  • Sequential transfers
  • AHB-Lite Specification
  • Universal Serial Bus OTG Controller
  • Ethernet MAC
  • CAN Controller
  • MMUART Peripherals
  • Serial Peripheral Interface Controller (SPI)
  • Inter-Integrated Circuit Peripherals (I²C)
  • MSS GPIO
  • Communication Block
    • Architecture Overview
    • CoreSysServices Soft IP
    • How to use the communication block
  • Real-Time Controller
  • System Timer
  • Watchdog Timer
  • ECC System Service
Exercise:  Programming using UART interface
Exercise:  MSS CAN drivers and APIs
Exercise:  Programming using USB OTG Controller Interface
Exercise:  Using ECC System Service
Exercise:  FreeRTOS and LWIP Project
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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