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U2UVM
Universal verification methodology

Objectives

  • Understand the role of UVM in modern verification environments
  • Learn UVM architecture and testbench structure
  • Master UVM components (test, env, agent, driver, monitor, sequencer, scoreboard)
  • Understand UVM phasing mechanism and simulation flow
  • Use UVM factory for flexible and reusable testbench design
  • Apply configuration and resource databases effectively
  • Implement transaction-level communication using TLM
  • Develop sequences and control stimulus generation
  • Build reusable and scalable UVM verification environments
  • Use command-line options and reporting for debugging
  • Understand and apply UVM Register Abstraction Layer (RAL)
  • Apply advanced UVM features and best practices
  • Theoretical course
    • PDF course material (in English)
    • The trainer to answer trainees’ questions during the training and provide technical and pedagogical assistance
  • Practical activities
    • Practical activities represent from 40% to 50% of course duration
    • Example code, labs and solutions
    • Use of industry-standard tools such as ModelSim, QuestaSim, or Vivado Simulator for simulation and debugging
  • Strong knowledge of SystemVerilog
  • Understanding of object-oriented programming (OOP)
  • Familiarity with digital design and RTL concepts
  • Basic programming knowledge (C/C++ or similar is a plus)
  • Basic knowledge of testbench architecture
  • Prior exposure to simulation and debugging tools
  • Any embedded systems engineer or technician with the above prerequisites.
  • The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
  • Trainee progress is assessed in two different ways, depending on the course:
    • For courses lending themselves to practical exercises, the results of the exercises are checked by the trainer while, if necessary, helping trainees to carry them out by providing additional details.
    • Quizzes are offered at the end of sections that do not include practical exercises to verifythat the trainees have assimilated the points presented
  • At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
    • In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Course Outline

  • What is UVM
  • Evolution OVM to UVM
  • UVM architecture overview
  • UVM testbench structure
  • UVM hierarchy
Exercise:  First sample UVM example
  • Overview of UVM Components
  • Base class
  • Core Components
    • Test
    • Environment
    • Agent
    • Driver
    • Monitor
    • Sequencer
    • Scoreboard
  • Component communication
    • TLM Connections
    • Analysis port
Exercise:  Build a simple UVM testbench
Exercise:  Run a basic simulation
  • Overview of UVM phases
  • Build-time phases
    • Build phase
    • Connect phase
    • End of elaboration phase
  • Run-time phase
    • Start of simulation phase
    • Run phase
    • Extract phase
    • Check phase
    • Report phase
  • Phase mechanism
    • Objections
    • Phase synchronization
  • Factory overview
  • Why factory
  • Factory Mechanism
    • Registration
    • Creation
    • Overrides
      • Type override
      • Instance override
    • Factory classes
      • UVM object wrapper
      • Registry classes
    • Factory Debugging
Exercise:  Register UVM components using factory
Exercise:  Create components
Exercise:  Apply type and instance overrides
Exercise:  Debug factory behavior
  • Configuration database
  • Resource database
  • Setting and getting configuration
  • Hierarchical configuration
  • TLM overview
  • TLM interfaces
  • Communication types
    • Blocking transport
    • Non-blocking transport
    • Analysis communication
  • Ports / Export / Imps
    • Uni-directional
    • Bi-directional
    • Broadcast
    • TLM FIFOs
Exercise:  Connect driver and sequencer using TLM
Exercise:  Use analysis port between monitor and scoreboard
Exercise:  Implement FIFO-based communication
Exercise:  Create Coverpoints, Bins (including illegal bins)
Exercise:  Add cross coverage
Exercise:  Run simulation and analyze coverage results
  • Sequence overview
  • UVM Sequence item
  • Sequencer
    • Arbitration
    • Communication with drivers
  • Sequence Execution
    • Start method
    • Virtual Sequences
  • UVM object
  • UVL Transaction
  • UVM Sequencer item
  • UVM Report Object
  • Utility Methods
Exercise:  Create sequence item and sequence
Exercise:  Send transaction to driver
Exercise:  Implement virtual sequence
  • Testbench architecture
  • Connecting Components
  • Reusable Agents
Exercise:  DUT integration
Exercise:  Driver implementation
Exercise:  Monitor implementation
Exercise:  Scoreboard design
Exercise:  Test creation
Exercise:  Running simulation
  • UVM command-line arguments
  • Verbosity control
  • Runtime configuration
  • Debug options
  • Reporting control
  • RAL overview
  • Register model
  • Register access methods
  • Frontdoor vs backdoor
  • RAL integration
  • Virtual interfaces
  • Callbacks
  • UVM reporting
  • Debugging techniques
  • Performance optimization
  • Build a complete UVM environment for a simple DUT:
    • Driver + Monitor + Scoreboard
    • Sequences
    • Functional checking
Duration
5 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 25 April 2026

Booking one of our trainings is subject to our General Terms of Sales

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