Formation LPC21XX/LPC22XX microcontroller implementation | Ac6 Training

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ac6 › ac6-training › Processors › NXP › LPC21XX/LPC22XX microcontroller implementation
Renseignements
NP1LPC21XX/LPC22XX microcontroller implementation
This course covers NXP ARM-based MCU family

Objectives

  • The course details the hardware implementation of the LPC2294 microcontrollers.
  • The boot sequence and the clocking are explained.
  • The training helps to become familiar with the development environment chosen by the customer.
  • Practical labs on integrated peripherals are based on I/O functions provided by NXP.
  • The course focuses on the low level programming of the ARM7TDMI core.
  • The course provides examples of internal peripheral software drivers.

  • Note that ACSYS does not sell emulation probes and IDEs. Consequently this course has not been designed to convince attendees to buy a particular IDE. The unique objective consists in providing sufficient knowledge to attendees so that they can successfully design a system based on LPC21XX/LPC22XX.

  • This course has been delivered several times to companies developing embedded systems, such as voltage counters.
A lot of programming examples have been developed by ACSYS to explain the boot sequence, the vector table and the operation of embedded peripherals.
•  They have been developed with 2 different IDEs : Keil and IAR.
•  Consequently for on site course, it is up to the customer to select the IDE under which labs will be run.
A more detailed course description is available on request at training@ac6-training.com
  • This course provides an overview of the ARM7TDMI core. Our course reference cours R1 - ARM7/9 implementation details the operation of this core.
  • The following course could be of interest:
  • Cours théorique
    • Support PDF (en anglais), imprimé en présentiel ; à distance via Teams.
    • Assistance du formateur tout au long de la formation.
  • Chaque session débute par un point avec les stagiaires.
  • Tout ingénieur ou technicien en systèmes embarqués possédant les prérequis ci-dessus.
  • Les prérequis sont évalués avant la formation.
  • Les progrès sont évalués par des quizz en fin de sections.
  • Chaque stagiaire reçoit une attestation de réussite.
  • En cas de prérequis manquant, une formation différente ou complémentaire est proposée.

Plan du cours

  • ARM core based architecture
  • ARM7 local bus
  • AMBA AHB/APB internal buses
  • The main three blocks : platform, core and input / output peripherals
  • APB Bridges
  • Memory mapping, internal flash (2294) and SRAM
  • Presentation of the core, architecture and programming model
  • Operating modes : user, system, super, IRQ, FIQ, undef and abort
  • Pipeline, calculation of the CPI
  • Effects of branches and exceptions on the performance
  • ALU data path
  • Parameterizing the linker to define sections
  • Branch instructions, implementation of C call and return statements, long branch veneers
  • ARM vs Thumb instruction sets, interworking
  • ARM instruction set
  • Inline barrel shifter
  • Access to memory-mapped locations, addressing modes
  • Arithmetical and logic instructions
  • Thumb instruction set, highlighting restrictions with regard to ARM instruction set
  • Compiler hints and tips, optimisations supported by RVCT
  • Stack management
  • Benefits of condition set capability in ARM state
  • C-to-Assembly interface, ATPCS specification
  • Reset
  • FIQ vs IRQ
  • Exception return instructions
  • Latency estimation, impact of load and store multiple instructions
  • Organization of the handler table, priority decoder, pre-emption and nesting
  • ISR header and footer routines
  • Development of a generic exception handler
  • JTAG interface
  • Debug facilities, hardware breakpoint
  • Executing code from RAM to take benefit of software breakpoints
  • Assigning a priority to each interrupt source
  • Steering external interrupts and local interrupts to either the core FIQ or IRQ
  • Developing a generic interrupt handler performing nesting according to peripheral priorities defined by the user
  • Integrated timers
  • Using timers to understand the operation of the VIC
  • Pin connect block
  • Clocking
  • Reset and wake-up timer
  • Low power modes
  • Watchdog timer
  • Real-Time clock
  • Organization
  • Erase sequence
  • Program sequence
  • In system programming via serial port
  • On-chip bootloader
  • Address decoding
  • Chip-select registers
  • Parameterizing the memory bank registers to support external burst flash
  • I2C basics
  • I2C controller
  • UART controller
  • SPI and SSP interfaces
  • CAN protocol basics
  • CAN controller (2294)
Durée
4 jours
Renseignements

Ce cours peut être organisé sur demande. Cliquez sur le bouton 'Renseignements' pour nous contacter.

Plus d'information

Pour vous enregistrer ou pour toute information supplémentaire, contactez nous par email à l'adresse info@ac6-formation.com.

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Ce cours peut être dispensé dans notre centre de formation près de Paris ou dans vos locaux, en France ou dans le monde entier.

Les sessions inter-entreprises programmées sont ouvertes dès deux inscrits. Sous condition d'un dossier complet, les inscriptions sont acceptées jusqu'à une semaine avant le début de la formation.

Dernière mise à jour du plan de cours : 20 mai 2026

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