| FF4 | MCF548x implementation |
This course covers MCF548X ColdFire MCUs, for instance the MCF5485
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Objectives
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- Experience of a 32 bit processor or DSP is mandatory.
- Ethernet and switching, reference N1 - Ethernet and switching course
- PCI 3.0, reference IC1 - PCI 3.0 course
- USB 2.0, reference IP2 - USB 2.0 course
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CAN bus, reference IA1 - CAN bus course
- Theoretical course
- PDF course material (in English) supplemented by a printed version for face-to-face courses.
- Online courses are dispensed using the Teams video-conferencing system.
- The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
- At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- ColdFire core versions
- Architecture of a typical 548X board
- Mapping of internal resources
- Pipeline basics
- Description of assembly instructions
- Floating Point Unit description
- Mac instructions, implementation of a fixed point DFT
- ColdFire instruction set architecture enhancements
- Stack management, subroutine call and return
- C to assembly interface, organization of the stack frame
- Position dependent code vs position independent code
- Section definition
- Exception management : vector table, priority, masking, precise faults
- Memory Management Unit : translation and access control, process protection
- TLB initialization
- Cache basics
- 32-kB cache data and instruction, a four-way set associative organization
- Cache coherency and invalidation, software control
- Internal 32-kB SRAM, initialization code
- Power management
- Intrusive vs non-intrusive debug
- BDM port
- Hardware breakpoints
- Trace port
- Reset sources
- Clocking, system clock generation, PLL control, loss of clock detection
- Reset control flow
- Requirements of the boot routine
- System Control Module
- Internal bus arbitration
- The interrupt controllers : vectorized vs auto-vectorized mode, edge Port Module
- Electrical specification, supply voltage sequencing
- Flexbus
- DDR SDRAM basics
- DDR SDRAM Controller
- PCI Controller
- Error management
- Programmable Interrupt Timer Modules
- General Purpose Timer Modules
- Input capture capability
- DMA task memory
- DMA sources
- Transfer control descriptors
- The PSC Module
- The DSPI
- The I2C controller
- The FlexCAN controller
- The Fast Ethernet Controller
- The USB 2.0 device controller
- Crypto-channels
- ARC four execution unit
- Multi-function data packet descriptors
Duration
4 days
Cost
1950 € HT
Calendar
To book a training session or for more information, please contact us on info@ac6-training.com.
Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.
You can also fill and send us the
registration form
This course can be provided either remotely, in our Paris training center or, worldwide, on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 2 working days before the course start (1 week for face-to-face courses).
Booking one of our trainings is subject to our
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