Is this course available online?

Yes, this course is available both on-site and online (via Microsoft Teams).

What are the prerequisites for this course?

Basic knowledge of digital design concepts (combinational and sequential logic) Familiarity with Verilog or VHDL (RTL coding fundamentals) Understanding of simulation concepts and waveform analysis Basic programming knowledge (C/C++ or similar is a plus) Familiarity with FPGA or ASIC design flow is recommended but not mandatory

SystemVerilog Training

Objectives

Understand the role of SystemVerilog in modern digital design and verification environments
Differentiate between simulation and synthesis, and apply appropriate coding practices
Master SystemVerilog data types, including integral, composite, and dynamic structures
Develop efficient RTL code using procedural blocks and proper assignment techniques
Apply control flow, parallel processing, and casting for robust hardware modeling
Design scalable systems using modules, interfaces, packages, and hierarchical constructs
Understand simulation scheduling semantics and avoid race conditions in designs
Apply object-oriented programming concepts for verification using classes and inheritance
Create constrained-random test scenarios using randomization and constraints
Measure and improve design quality using functional and code coverage techniques
Use assertions to validate design behavior and detect errors early in simulation
Develop structured test benches using interfaces and basic verification components
Understand the fundamentals of UVM and its role in modern verification methodologies

Course environment

Theoretical course

PDF course material (in English)
The trainer to answer trainees questions during the training and provide technical and pedagogical assistance

Practical activities

Practical work with ModelSim QuestaSim and Vivado Simulator.
Practical activities represent from 40% to 50% of course duration
Example code, labs and solutions

Prerequisite

Basic knowledge of digital design concepts (combinational and sequential logic)
Familiarity with Verilog or VHDL (RTL coding fundamentals)
Understanding of simulation concepts and waveform analysis
Basic programming knowledge (C/C++ or similar is a plus)
Familiarity with FPGA or ASIC design flow is recommended but not mandatory

Target Audience

Any embedded systems engineer or technician with the above prerequisites.

Evaluation modalities

The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
Trainee progress is assessed in two different ways, depending on the course:

For courses lending themselves to practical exercises, the results of the exercises are checked by the trainer while, if necessary, helping trainees to carry them out by providing additional details.
Quizzes are offered at the end of sections that do not include practical exercises to verifythat the trainees have assimilated the points presented

At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.

In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Exercise:	Declare and manipulate:
	•	A packed vs unpacked array
	•	A struct representing a packet (addr, data, valid)
	•	A queue and perform push/pop operations
Exercise:	Use an associative array to count occurrences of values
Exercise:	Simple mailbox communication between two processes

Exercise:	Implement a counter module using:
	•	always_ff and non-blocking assignments
Exercise:	Compare blocking vs non-blocking behavior using simulation
Exercise:	Write a task to generate a pulse signal
Exercise:	Use fork...join to run parallel stimulus threads

Exercise:	Create an interface to connect DUT and testbench
Exercise:	Use generate to instantiate multiple modules
Exercise:	Organize code using a package

Exercise:	Write a small testbench showing:
	•	Race condition between blocking/non-blocking assignments
Exercise:	Observe waveform differences in:
	•	Active vs NBA regions
Exercise:	Fix the race condition using proper coding style

Exercise:	Create a transaction class (addr, data, control)
Exercise:	Implement:
	•	Constructor
	•	Inheritance
Exercise:	Demonstrate polymorphism using virtual methods

SystemVerilog Training | Ac6 Training

Course Outline

Exercise:	Create a random transaction with:
	•	Constraints on address range
	•	Distribution (dist) constraint
Exercise:	Use randomize() and display results
Exercise:	Add pre_randomize() and post_randomize() hooks

Exercise:	Create:
	•	Coverpoints
	•	Bins (including illegal bins)
Exercise:	Add cross coverage
Exercise:	Run simulation and analyze coverage results

Exercise:	Write assertions for:
	•	Valid signal must follow enable
	•	FIFO never overflows/underflows

Exercise:	Build a simple testbench:
	•	Driver → DUT → Monitor
Exercise:	Use an interface + virtual interface
Exercise:	Send transactions from driver to DUT
Exercise:	Capture outputs using monitor

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