Cette formation est-elle disponible en ligne ?

Oui, cette formation est disponible en présentiel et en ligne (visioconférence Teams).

Quels sont les prérequis pour cette formation ?

Basic knowledge of digital design concepts (combinational and sequential logic) Familiarity with Verilog or VHDL (RTL coding fundamentals) Understanding of simulation concepts and waveform analysis Basic programming knowledge (C/C++ or similar is a plus) Familiarity with FPGA or ASIC design flow is recommended but not mandatory

Formation SystemVerilog

Objectives

Understand the role of SystemVerilog in modern digital design and verification environments
Differentiate between simulation and synthesis, and apply appropriate coding practices
Master SystemVerilog data types, including integral, composite, and dynamic structures
Develop efficient RTL code using procedural blocks and proper assignment techniques
Apply control flow, parallel processing, and casting for robust hardware modeling
Design scalable systems using modules, interfaces, packages, and hierarchical constructs
Understand simulation scheduling semantics and avoid race conditions in designs
Apply object-oriented programming concepts for verification using classes and inheritance
Create constrained-random test scenarios using randomization and constraints
Measure and improve design quality using functional and code coverage techniques
Use assertions to validate design behavior and detect errors early in simulation
Develop structured test benches using interfaces and basic verification components
Understand the fundamentals of UVM and its role in modern verification methodologies

Course environment

Theoretical course

PDF course material (in English)
The trainer to answer trainees questions during the training and provide technical and pedagogical assistance

Practical activities

Practical work with ModelSim QuestaSim and Vivado Simulator.
Practical activities represent from 40% to 50% of course duration
Example code, labs and solutions

Prerequisite

Basic knowledge of digital design concepts (combinational and sequential logic)
Familiarity with Verilog or VHDL (RTL coding fundamentals)
Understanding of simulation concepts and waveform analysis
Basic programming knowledge (C/C++ or similar is a plus)
Familiarity with FPGA or ASIC design flow is recommended but not mandatory

Environnement du cours

Cours théorique

Support imprimé et PDF (en anglais).
Assistance du formateur tout au long de la formation.

Activités pratiques (40-50% de la durée)

Exemples de code, exercices et solutions.
Un PC (un par binôme au-delà de 6 stagiaires) avec carte cible si nécessaire.

Machine virtuelle préconfigurée téléchargeable pour refaire les TP après le cours.
Chaque session débute par un point avec les stagiaires.

Audience visée

Tout ingénieur ou technicien en systèmes embarqués possédant les prérequis ci-dessus.

Modalités d'évaluation

Les prérequis sont évalués avant la formation.
Les progrès sont évalués par le formateur via les exercices pratiques, et par des quizz pour les sections sans exercices.
Chaque stagiaire reçoit une attestation de réussite.
En cas de prérequis manquant, une formation différente ou complémentaire est proposée.

Exercise :	Declare and manipulate:
	•	A packed vs unpacked array
	•	A struct representing a packet (addr, data, valid)
	•	A queue and perform push/pop operations
Exercise :	Use an associative array to count occurrences of values
Exercise :	Simple mailbox communication between two processes

Exercise :	Implement a counter module using:
	•	always_ff and non-blocking assignments
Exercise :	Compare blocking vs non-blocking behavior using simulation
Exercise :	Write a task to generate a pulse signal
Exercise :	Use fork...join to run parallel stimulus threads

Exercise :	Create an interface to connect DUT and testbench
Exercise :	Use generate to instantiate multiple modules
Exercise :	Organize code using a package

Exercise :	Write a small testbench showing:
	•	Race condition between blocking/non-blocking assignments
Exercise :	Observe waveform differences in:
	•	Active vs NBA regions
Exercise :	Fix the race condition using proper coding style

Exercise :	Create a transaction class (addr, data, control)
Exercise :	Implement:
	•	Constructor
	•	Inheritance
Exercise :	Demonstrate polymorphism using virtual methods

Formation SystemVerilog | Ac6 Training

Objectives

Course environment

Prerequisite

Environnement du cours

Audience visée

Modalités d'évaluation

Plan du cours

First Day

Introduction

Data Types

Procedural & Process Blocks

Second Day

Design Hierarchy & RTL Constructs

Scheduling Semantics

Third Day

Classes

Randomization

Coverage

Fourth Day

Assertions

Interfaces & Testbench Architecture

Introduction to UVM

Exercise :	Create a random transaction with:
	•	Constraints on address range
	•	Distribution (dist) constraint
Exercise :	Use randomize() and display results
Exercise :	Add pre_randomize() and post_randomize() hooks

Exercise :	Create:
	•	Coverpoints
	•	Bins (including illegal bins)
Exercise :	Add cross coverage
Exercise :	Run simulation and analyze coverage results

Exercise :	Write assertions for:
	•	Valid signal must follow enable
	•	FIFO never overflows/underflows

Exercise :	Build a simple testbench:
	•	Driver → DUT → Monitor
Exercise :	Use an interface + virtual interface
Exercise :	Send transactions from driver to DUT
Exercise :	Capture outputs using monitor

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