Cortex-M1 implementation Training | Ac6 Training

ac6-training, un département d'Ac6 SAS
EN
✓EnglishFrench
go-up

ac6 › ac6-training › Processors › ARM Cores › Cortex-M1 implementation
Inquire
RM1Cortex-M1 implementation
This course covers the Cortex-M1 ARM core targetting FPGA SoCs

Objectives

  • This course is split into 3 important parts:
    • Processor architecture
    • Software implementation
    • Hardware implementation.
  • A tutorial has been developed by ACSYS to facilitate the understanding of Cortex-M1 low level programming, therefore labs can be replayed after the course.
  • The course explains how to design a SoC based on Cortex-M1, clarifying the operation of the interconnect and the debug facilities integrated in the CPU.
A more detailed course description is available on request at training@ac6-training.com
  • Knowledge of ARM7/9.
  • This course does not include chapters on low level programming.
    • ACSYS offers a large set of tutorials to become familiar with RVDS, assembly level programming, compiler hints and tips.
  • More than 12 correct answers to Cortex-R prerequisites questionnaire.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by quizzes at the end of sections.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • Programmer's model
  • Fixed memory map
  • Privilege, modes and stacks
  • Memory Protection Unit
  • Interrupt handling
  • Nested Vectored Interrupt Controller [NVIC]
  • Power management
  • Debug
  • Datapath and pipeline
  • Write buffer
  • Bit-banding
  • System timer
  • State, privilege and stacks
  • System control block
  • Different level of debug implementation
  • Exception behavior, exception return
  • Non-maskable exceptions
  • Privilege, modes and stacks
  • Fault escalation
  • Vector table
  • Data processing instructions
  • Branch and control flow instructions
  • Memory access instructions
  • Exception generating instructions
  • If...then conditional blocks
  • Exclusive load and store instructions
  • Accessing special registers
  • Memory barriers and synchronization
  • Interrupt entry / exit, timing diagrams
  • Tail chaining
  • Interrupt response, pre-emption
  • Interrupt prioritisation
  • Interrupt implementation configurability, impact on core size
  • Memory types, restriction regarding load / store multiple
  • Device and normal memory ordering
  • Access order
  • Memory barriers
  • Cortex-M1 debug features
  • Monitor mode
  • Flash patch and breakpoint features
  • Data watchpoint and trace
  • DWT registers
  • AHB-Access Port
  • Functional Integration
  • Clocking
  • Reset
  • AHD and Debug interfaces
  • Synthesis, Place and Route
  • Sign-Off
  • Implementation flow
  • Configuration options
  • RTL Validation
  • Synthesis
  • Place and route
  • Qualification
  • Purpose of this specification
  • Example of SoC based on AMBA specification
  • Differences between AMBA2.0 and AMBA3.0
  • Centralized address decoding
  • Address gating logic
  • Arbitration, bus parking
  • Single-data transactions
  • Sequential transfers
  • Retry response
  • Split response
  • AHB-lite specification
  • Read timing diagram
  • Write timing diagram
  • Operation of the AHB-to-APB bridge
  • APB3.0 new features
  • Clocking and reset
  • Bus interfaces , AMBA-3 compliance
  • Debug interface, AHB-AP programming interface
  • Connection to the TPIU
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

Related Courses