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MPC5674F implementation

This course covers NXP Qorivva MPC5673F and MPC5674F

Objectives

  • This course has 6 main objectives:
    • Detailing the hardware implementation of the MPC56XX
    • Parameterizing the internal interconnect and sophisticated eDMA controllers
    • Focusing on the various operation modes supported by the eQADC
    • Describing the timer units, including eTPU2
    • Describing the communication interfaces, including FlexCAN and FlexRay
    • Studying the debug capabilities offered by the Nexus interface.

  • Products and services offered by AC6:
    • AC6 is able to assist the customer by providing consultancies
    • Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
A lot of programming examples have been developed by AC6 to explain the boot sequence and the operation of complex peripherals.
They have been developed with Diab Data compiler and are executed with TRACE32 Lauterbach debugger.
A more detailed course description is available on request at training@ac6-training.com
This document is necessary to tailor the course to specific customer needs and to define the exact schedule.
  • Experience of a 32-bit processor or DSP is mandatory.
  • Note that the e200z7 Power core is covered in a separate course reference FCC3 - e200z7 implementation course.
  • The following courses could be of interest:
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • Compatibility with MPC55XX family
  • Memory mapping
  • e200z7 core integration
  • Power management controller
  • Reset
  • Clocking
  • Boot assist module (BAM)
  • Pad configuration control for each pad
  • System reset monitoring and generation
  • External interrupt pins
  • General Purpose Input Output setting
  • Internal peripheral multiplexing
  • Multiplexed address/data transfers
  • Chip-select programming
  • Burst support
  • Dynamic calibration with up to 4 chip-selects
  • 64 analog channels, differential conversions
  • ADC clock and conversion speed
  • ADC calibration feature
  • MAC unit and operand data format
  • Variable gain amplification
  • CFIFO0 streaming mode
  • 8 decimation filters
  • Temperature sensor
  • Time stamp information
  • Trigger sources
  • External multiplexing
  • Interrupt or DMA request generation
  • Crossbar switch
  • Peripheral Bridge
  • Memory Protection Unit
  • Status information regarding platform memory errors
  • 256-KB on-chip SRAM
  • 4-MB on-chip flash
  • Priority-based preemptive scheduling
  • Preemptive prioritized interrupt requests to processor
  • Software-configurable priorities of ISR or tasks
  • Software vector mode vs hardware vector mode
  • DMA request assignments
  • Transfer control descriptors
  • Channel-to-channel linking mechanism
  • Peripheral-paced hardware requests
  • Channel arbitration
  • Scatter/gather DMA processing
  • Modulo feature
  • Introduction to LIN specification
  • Idle line detection
  • LIN master node functionality
  • Detection of bit errors, physical bus errors and checksum errors
  • DMA support for both transmit and receive data
  • Hardware interface
  • 64 message buffers of zero to eight bytes data length
  • Individual Rx mask registers per message buffer
  • Powerful Rx FIFO ID filtering
  • Management of remote frames, overload frames
  • Listen-only mode capability
  • Time stamp based on 16-bit free-running timer
  • Serial Peripheral Interface (SPI) configuration
  • Deserial Serial Interface (DSI) configuration
  • Combining Serial Interface (CSI) configuration
  • Enhanced Deserial Serial Interface (DSI) configuration
  • Queued operation
  • Hardware interface
  • FlexRay memory layout
  • Message buffer concept
  • Buffer locking scheme
  • Message buffer states
  • Individual message buffer reconfiguration supported
  • Filtering on FrameID, ChannelID, MessageID
  • Slot error counters
  • System Timer Module
  • Periodic Interrupt Timer, Real Timer Interrupt
  • SWT
  • Shared time bases with the eTPU
  • Output Pulse Width Modulation (OPWM) mode
  • Input Pulse-Width Measurement (IPWM) mode
  • Pulse/Edge Accumulation (PEA) mode
  • Quadrature decode (QDEC) mode
  • Windowed Programmable Time Accumulation (WPTA) mode
  • Output Pulse Width and Frequency Modulation (OPWFM) mode
  • Pulse-Width and Frequency Modulation Buffered (OPWFMB) mode
  • Center Aligned Output Pulse Width Modulation with Dead Time (OPWMC) mode
  • Center-Aligned Output PWM Buffered with Dead Time (OPWMCB) mode
  • Hardware interface
  • Time base
  • Event-triggered microengine
  • Functions and threads
  • Host interface
  • Scheduling channel service requests
  • Parameter sharing and coherency
  • Implementing functions developed by NXP
  • Introduction to NEXUS specification
  • Data trace via data write messaging and data read messaging
  • Ownership trace via ownership trace messaging
  • Program trace via branch trace messaging
  • Watchpoint messaging via the auxiliary port
  • Run-time access to the on-chip memory
Duration
4 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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