Kinetis MCU Implementation Training | Ac6 Training

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FK1Kinetis MCU Implementation
This course covers all NXP MCUs belonging to the Kinetis families K10, K20, K30, K40 and K60

Objectives

  • This course has 5 main objectives:
    • Describing the hardware implementation and highlighting the pitfalls
    • Describing the ARM Cortex-M4 core architecture
    • Becoming familiar with the IDE and low level programming
    • Describing the units which are interconnected to other modules, such as clocking, interrupt controller and DMA controller, because the boot program generally has to modify the setting of these units
    • Describing independent I/O modules and their drivers.
  • Note that this course has been designed from the architecture of the most complex Kinetis device, the K60.
    • Consequently, a chapter has been designed by Acsys for each possible integrated IP.
    • So the customer can build its own course outlines from the topics described hereafter.

  • Products and services offered by ACSYS:
    • ACSYS has developed FFTs (floating-point and fixed-point) optimized for ARM cores, based on SIMD instructions supported by the Cortex-M4.
    • Contact training@ac6-training.com to obtain informations about the performance of these FFTs.
    • ACSYS is able to assist the customer by providing consultancies. Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
    • ACSYS has also an expertise in FreeRTOS or MQX porting and uIP /LWIP stack or Interniche stack integration.

A lot of programming examples have been developed by ACSYS to help the attendee to become familiar with the IDE he has chosen.
That is why the labs included in this course can be compiled and executed under 3 possible IDEs: IAR, CodeWarrior and GCC / Lauterbach Trace32.
A more detailed course description is available on request at training@ac6-training.com
This document is necessary to tailor the course to specific customer needs and to define the exact schedule.

  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by quizzes at the end of sections.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • ARM core based architecture
  • Description of K10, K20, K30, K40 and K60 SoC architecture
  • Clarifying the internal data and instruction paths: AHB-lite interconnect, peripheral buses, AIPD bridges
  • AMBA-to-IPS Re-use IP: ColdFire (AIPS) Controller
  • Integrated memories
  • SoC mapping
  • V7-M core family
  • Core architecture
  • Freescale on-chip instruction and data cache
  • Thumb-2 instruction set
  • Exception behavior
  • Basic interrupt operation, micro-coded interrupt mechanism
  • Memory Protection Unit
  • Multiply instructions
  • Packing / unpacking instructions
  • SIMD packed add/sub instructions
  • SIMD combined add/sub instructions
  • SIMD multiply and multiply accumulate instructions
  • SIMD sum absolute difference instructions
  • SIMD select instruction
  • Saturation instructions
  • Floating point unit
  • Cortex Microcontroller Software Interface Standard (CMIS)
  • Acsys covers 3 iDEs: CodeWarrior, IAR and GCC / Lauterbach
  • Thus the customer has just to indicate which one he has chosen
    • Getting started with the IDE
    • Parameterizing the compiler / linker
    • Creating a project from scratch
    • C start program
  • Debug interface
  • Programming
  • Reset
  • Clocking
  • Operation modes
  • Crossbar switch
  • Hardware Memory Protection Unit
  • eDMA
  • Power pins
  • Pinout
  • GPIO module
  • Flex memory, this module is not implemented in all Kinetis devices
  • Internal SRAM
  • Each Kinetis family supports either a subset or all the following controllers
  • FlexBus
  • eSDHC
  • NAND flash controller
  • DRAM controller
  • Low Power Oscillator
  • COP
  • External Watchdog Monitor
  • Periodic Interrupt Timer
  • Low Power Timer
  • Flex Timer
  • Carrier Modulator Transmitter
  • 16-bit Analog-to-Digital Converter and Programmable Gain Amplifier
  • 12-bit Digital-to-Analog Converter
  • Voltage Reference VREF
  • High-Speed Comparator HSCMP
  • Programmable Delay Block PDB
  • Hardware Cyclic Redundancy Check
  • Memory-Mapped Cryptographic Acceleration Unit (MMCAU)
  • Pseudo Random Number Generator
  • Secure Real Time Clock
  • DryIce and Tamper Detect
  • Cryptographic Acceleration Unit
  • DSPI
  • UART
  • I2C
  • CAN modules
  • USB
  • Fast ethernet with IEEE1588
  • ISO7816 smartcard interface
  • I2S audio interface
  • Segment LCD controller
  • Graphics LCD controller
  • Capacitive touch sensing
Duration
5 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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