ac6-training, un département d'Ac6 SAS
EN
✓EnglishFrench
go-up

ac6 › ac6-training › Processors › NXP › DSP563XX implementation
Inquire
FD2

DSP563XX implementation

This course covers the 563XX 24-bit DSP NXP family

Objectives

  • The course explains how to design a 56L307 based board
  • Optimized coding examples are described
  • A generic interrupt handler is introduced
  • DMA channels are viewed in detail
  • The course focuses on the serial ports SCI and ESSI
  • Practical exercices are executed on a 56L307 board
A lot of programming examples have been developed by ACSYS to explain how to write optimized code.
•  They have been developed with CodeWarrior compiler and are executed under CodeWarrior debugger.
A more detailed course description is available on request at training@ac6-training.com
  • Basic knowledge of signal processing.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • Arithmetic processing of real-time signals
  • Modified dual Harvard architecture : the X-memory and the Y-memory
  • MAC operation
  • DSP 563XX family introduction
  • Core buses
  • Processing states
  • Reset
  • 56L307 mapping
  • The Data ALU
  • The Address Generation Unit
  • The Program Control Unit
  • The instruction set
  • C-to-assembly interface
  • The PLL
  • The 563XX instruction cache
  • Exception management
  • The debugging support
  • JTAG use to access the OnCE
  • External memory addressing
  • Arbitration protocol
  • SRAM interface
  • DRAM basics
  • DRAM interface
  • Overlap between DMA channel and core
  • Channel priority
  • Triggering modes
  • Circular buffer management
  • Host interface description
  • Transfer modes
  • Handshaking protocols
  • DMA access to HTX and HRX data registers
  • Boot up using the HIO8 host port
  • Programming model : host-side and DSP-side register banks
  • Timer related pins
  • Triple timer modes
  • Event capture
  • Signal width / period measuring
  • PWM
  • Watchdog modes
  • ESSI signals
  • Network mode
  • On-Demand mode
  • ESSI exceptions
  • Transmit and receive sequences
  • SCI block diagram
  • Asynchronous vs synchronous operation modes
  • Baud rate selection
  • Bootstrap loading from the SCI
  • Asynchronous transmit and receive sequences
  • PMB interface, FMAC unit, FDM bank, FCM bank
  • FIR filter options
  • IIR filter options
  • Multichannel mode
  • Input scaling
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

On the same topic:

Yocto or Buildroot: how to choose for your embedded Linux project

Related Courses