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eTPU programming

This course covers eTPU code generation and simulation

Objectives

  • The course explains the CPU-like TPU architecture.
  • CPU-to-TPU interface is detailed.
  • The course highligths all channel operation modes.
  • The course focuses on various fields of the instructions enabling concurrency.
  • The scheduler priority algorithm is detailed in order to estimate the worst case latency for channel service.
  • Micro-coding and debugging an application composed of several states is explained through practical examples.

  • This course has been delivered several times to companies developing automotive systems.
A lot of programming examples have been developed by ACSYS to explain the eTPU operation.
•  They have been developed with Ashware tools.
A more detailed course description is available on request at training@ac6-training.com
  • Basic knowledge about microprocessor architecture, hardware timer and assembler instructions and directives.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • Locating the TPU in different components proposed by NXP
  • Objectives of a such approach
  • Quick presentation of standard functions
  • The various modules and interactions between them
  • Micro-engine
  • Ram
  • Host interface
  • Rom
  • Channel
  • Scheduler
  • Features
  • Block diagram
  • State at Reset
  • Configuring a channel
  • Transition event
  • Match event
  • Full default modes study
  • Channel link
  • Mapping
  • The addressing modes
  • Timing
  • Coherency
  • Sources of service requests
  • Requests hierarchy
  • Preemptivity
  • State selection
  • VLIW machine
  • Instruction format
  • Registers list
  • Execution unit hardware
  • Code condition latch
  • Channel selection
  • Loop
  • Arithmetic instructions
  • Multiply and Mac instructions
  • Pipeline
  • Branch chart
  • Conditional branches
  • Flush pipe or not
  • Repeat capabilities
  • Call and return instructions
  • Entry table chart
  • Scheduler behavior, inner channel priority management
  • Entry directive
  • Entry points general format
  • Sources of service request
  • Service requests priority
  • Selected state address generation
  • Priority scheme
  • Threads switch timing
  • Taking into consideration other requests
  • Access concurrency delay
  • This part may be tailored to customers needs during on-site trainings.
  • For instance developing a UART function with parity generation / checking can be used to understand all the previous topics.
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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