MPC8572E implementation

Objectives

• The course details the Ocean crossbar operation.
• Cache coherency protocol is introduced in increasing depth and the benefit of data stashing is explained.
• The e500 core is viewed in detail, especially the SPU that enables Floating point and vector processing.
• The boot sequence and clocking are explained.
• The course details the hardware implementation of the MPC8572E.
• A long introduction to DDR2/3 SDRAM operation is done before studying the DDR SDRAM controller.
• An in-depth description of the RapidIO port and the PCI-Express port is done.
• The course highlights both hardware and software implementation of gigabit / fast / Ethernet controllers.
• The course clarifies the operation of hardware acceleration mechanisms : Gigabit Ethernet TCP/IP offload engine, Pattern matcher and Table Lookup Unit.

• ACSYS has developed an optimized SPE based FFT coded in assembler language.
• Performance for 1024 complex floating point single precision samples is:
• - 91_386 core clock cycles without reverse ordering, 94_124 with reverse ordering
• Performance for 4096 complex floating point single precision samples is:
• - 470_778 core clock cycles without reverse ordering, 511_227 with reverse ordering
• for any information contact training@ac6-training.com