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ac6 >> ac6-training >> Processors >> NXP Power CPUs >> T1040 QorIQ implementation Download as PDF Write us

FCQ10 T1040 QorIQ implementation

This course covers NXP QorIQs T1020, T1022, T1040, T1042

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Objectives
  • This course has the following objectives:
    • Describing the hardware implementation, particularly the boot sequence and the DDR3 controller
    • Understanding the features of the internal interconnect and related units and mechanisms such as PAMU, CPC and stashing
    • Explaining the standard bus interface controllers, PCIe, USB, SATA and MMC-SD
    • Describing the units which are interconnected to other modules, such as clocking, interrupt controller and DMA controller, because the boot program generally has to modify the setting of these units
    • Clarifying the operation of the Datapath Acceleration Architecture that assists the processor core in taking in charge buffer allocation, queue management, frame management and particularly incoming frame classification, pattern searching, and encryption
    • Describing the various debug units and their utilization to fix errors in a multicore / multimaster SoC.
A more detailed course description is available on request at training@ac6-training.com
This document is necessary to tailor the course to specific customer needs and to define the exact schedule.
  • Theoretical course
    • PDF course material (in English) supplemented by a printed version for face-to-face courses.
    • Online courses are dispensed using the Teams video-conferencing system.
    • The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
  • At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
  • Any embedded systems engineer or technician with the above prerequisites.
  • The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
  • Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
  • At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
    • In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Course Outline

  • CoreNet coherency fabric
  • Coherency subdomains
  • Memory map, local access windows
  • Highlighting data paths inside the T104X, T102X
  • Application examples
  • Reset causes
  • Reset configuration words source
  • Pre-boot loader
  • PCIe configuration
  • Clocking, system clock domains
  • SerDes high speed lanes configuration
  • Advanced power management
  • Internal boot ROM, secure boot sequence
  • Security fuse processor
  • Code signing
  • External tamper detection
  • Run time integrity checker
  • Secure debug controller
  • Cache operation, write-through or write-back operation
  • Operation as memory-mapped SRAM
  • Partitioning between coherency domains
  • Stashing, address-based or CoreNet signalled
  • Soft error detection and correction
  • Controlling master access permissions through Logical I/O Device Number
  • Address translation
  • Data structures, Peripheral Access Authorization and Control Entry
  • Operation mode translation
  • Steps in processing of DSA operations by PAMU
  • PAMU gate closed state
  • Bridging agent
  • Transaction ordering
  • Resolution of coherency effects
  • Authorization, access control and address mapping of I/O-initiated transactions flowing into the CoreNet coherency domain
  • Open PIC architecture compatibility
  • Interrupt nesting
  • Message interrupts
  • e5500-to-e5500 interrupt capability
  • Description of the NS16452/16552 compliant Uarts
  • I2C protocol fundamentals: addressing, multimaster operation
  • Transfer timing diagrams, SCL and SDA pins
  • eSPI controller
  • Interface to SD and MMC cards
  • Transfer protocol, single block, multiple block read and write
  • Internal and external DMA capabilities
  • SD protocol unit
  • Host or device support
  • High-speed operation
  • EHCI support, scheduling the various transactions into frames
  • Endpoint configuration
  • Device operation
  • On-Die termination and calibration
  • DDR3 fly-by architecture, write leveling
  • Reset sequence, dynamic ODT, ZQ calibration
  • Bank activation, read, write and precharge timing diagrams, page mode
  • Initial configuration following Power-on-Reset
  • Address decode unit
  • Timing parameters programming
  • • Initialization routine
  • • Testing the memory using patterns
  • Functional muxing of pins between NAND, NOR, and GPCM
  • Normal GPCM FSM
  • Flexible timing control
  • NOR flash FSM
  • Configurable even/odd parity on address/data bus supported
  • NAND flash FSM
  • ONFI-2.0 asynchronous interface
  • ECC generation/checking
  • SLC and MLC Flash devices support with configurable page sizes
  • Scatter / gathering
  • Selectable hardware enforced coherency
  • Ability to start DMA from external 3-pin interface
  • Modes of operation, Root Complex / Endpoint
  • Transaction ordering rules
  • Programming inbound and outbound ATMUs
  • Benefits of MSIs
  • Low power management
  • Configuration, initialization
  • Support for SATA II extensions
  • Native command queuing, command descriptor
  • Standard ATA master-only emulation
  • Interrupt coalescing
  • Modes of operation
  • Area descriptor
  • Pixel structure
  • Alpha-blending
  • Chroma keying
  • Gamma correction
  • Internal DMA channels
  • Data formats
  • Frame formats
  • Packet walk through
  • DPAA Configuration and initialization
  • Objectives if this accelerator
  • Structure of frame queues
  • Active and suspended frame queues
  • Frame queue descriptor, frame queue descriptor cache
  • Frame queue state machine
  • Work queues and channels
  • Enqueue and dequeue portals
  • Utilization of rings
  • Dequeue dispatcher operation
  • Message ring
  • Congestion avoidance, Weighted Random Early Discard
  • Order definition point implementation
  • Objectives if this accelerator
  • Central resource pool management function
  • Per-pool stockpile
  • CoreNET software portals
  • Direct connect portals
  • Buffer Pool State Change Notifications
  • Objectives if this accelerator
  • FMAN submodules
  • Rx BMI features
  • Tx BMI features
  • Offline parsing, host command features
  • Frame processing manager
  • FMan controller
  • Parser
  • Key generator
  • Policer
  • Frame format with and without VLAN option
  • Connection to packet FIFO interface
  • Physical interfaces
  • 256-entry hash table for unicast and multicast
  • Accessing PHY registers
  • RMON statistic counters, carry registers
  • Client IEEE1588 timers
  • XAUI interface to PHY
  • Multicast address filtering
  • Dynamic inter packet gap (IPG) calculation
  • MAC address insertion
  • Support for VLAN
  • IEEE 1588 timestamping
  • Introduction to DES, 3DES and AES algorithms
  • Job management using QMan interface
  • Input / output rings
  • Cryptographic operations
  • Data movement, FIFOs
  • Scatter / gather DMA
  • Selecting the authentication / cryptographic algorithm
  • Run Time Integrity Checking
  • Example, implementing IPSec
  • Introduction to NEXUS specification
  • NEXUS Aurora link
  • Event processing unit
  • Watchpoint facility
  • Trace buffer
  • Event Combining for the Creation of Advanced Triggers
  • Cross-Functional Debug Components
  • DDR SDRAM interface debug, measuring per-master bandwidth
  • Integration in the T1040/T1020
  • Block diagram
  • Auto-negotiation
  • Flow control, priority based flow control (IEEE 802.1Qbb)
  • Energy Efficient Ethernet
  • Port trunking (link aggregation)
  • Frame Classification (QoS, VLAN), translation / remarking
  • Basic classification + advanced classification through IS1 TCAM
  • Security Enforcement, MAC/IP binding through IS2 TCAM
  • Dynamic Load Balancing policies, compliancy with Metro Ethernet Forum
  • L2 forwarding
  • Global storm policers for all the ingress traffic
  • Cut-through operation
  • Buffer management
  • Frame Reference management
  • Watermark programming and consumption monitoring
  • Shapers and schedulers for egress traffic
  • Deficit Weighted Round Robin algorithm
  • Rewriter, VLAN translation, push/ pop tags DSCP remapping, through ES0 TCAM
  • ES0 key
  • Green/Yellow departures
  • Statistics
  • IEEE802.1P and IEEE802.1Q implementation
  • Frame aging
  • Learning through Source MAC address
  • Multicast management, IGMP/MLD snooping
  • Adding entries by software in the forwarding table
  • Support of STP, RSTP, MSTP
  • Integrated RISC CPU
  • Communication between Host CPU and QE RISC CPU
  • Priority management
  • Steering the interrupt source to either Low priority or High priority input of the platform PIC
  • Serial DMA
  • QUICC engine external requests
  • NMSI vs TDM
  • Enabling connections to TSA or NMSI
  • Utilization of Buffer Descriptors
  • Chaining descriptors into rings
  • Parameter RAM independent of protocol
  • UCC as slow communications controllers, UART mode
  • UCC for fast protocols, virtual FIFOs
  • Flow control
  • Setting global parameters
  • Describing the parameter RAM
  • Transparent data encapsulation, frame sync and frame CRC
  • Describing the parameter RAM
  • Connecting TDM lines
  • Parameterizing the timings related to Rx/Tx clock, sync and data signals
  • Connecting the TDM line to UCC using Rx/Tx routing tables
  • Comparison with MCC and QMC
  • Connecting time-slots to logical channels through Rx/Tx routing tables
  • Implementing Rx/Tx channel buffers
  • Interrupt management
  • Channel-specific HDLC parameters
  • Per channel exception management
  • UMCC host commands