STM32G4 Training | Ac6 Training

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STR15STM32G4
This course descirbe the STM32G4 architecture and practical examples

Objectives

  • Understand the Cortex-M4F core, DSP and FPU basics.
  • Configure RCC and clocks; validate timing and prescalers.
  • Use GPIO/EXTI, timers, DMA/DMAMUX, and LPTIM/RTC.
  • Acquire high-rate analog data with ADC + DMA, oversampling, OPAMP/COMP, DAC.
  • Apply HRTIM for power/motor control; trigger ADC from PWM.
  • Accelerate math with CORDIC and FMAC; compare vs software.
  • Implement robust comms (USART, SPI, I²C, optional FDCAN).
  • Manage Flash/OB, watchdogs, reset causes; build a production checklist.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Practical activities (40-50% of duration)
    • Code examples, exercises and solutions.
    • Remote: one online Linux PC per trainee, with emulated or physical board as needed.
    • Face-to-face / on-site: one PC (one per two beyond six trainees), target board and install manual as needed.
  • Downloadable preconfigured VM to redo the labs afterwards.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by the trainer through the practical exercises, and by quizzes for sections without exercises.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • Core architecture
  • Programmer's model
  • Exceptions, NVIC priorities.
  • DSP instructions (SIMD/MACC).
  • FPU single-precision.
  • WFI/WFE basics.
Exercise:  Exception Management
Exercise:  SIMD demo
  • Bus matrix AHB/APB.
  • Flash/SRAM regions.
  • Peripheral address map.
  • UID / Flash size regs.
  • Option bytes (overview).
Exercise:  Map & IDs
  • HSI/HSE/PLL sources.
  • PLLs
  • SYSCLK mux, AHB/APB prescalers.
  • Kernel clocks (CCIPR).
  • MCO output, CSS.
Exercise:  Clock profiles
  • Modes: PP/OD, pulls.
  • Speed/drive strength.
  • AF mapping rules.
  • EXTI lines and priorities.
  • Safe I/O at reset.
Exercise:  GPIO / EXTI
  • PWM edge/center.
  • Input capture, one-pulse.
  • Encoder interface.
  • Master/slave triggers.
  • LPTIM for tickless.
Exercise:  PWM + capture
  • Stream/channel mapping.
  • Circular vs normal.
  • HT/TC/TE IRQs.
  • Throughput vs latency.
  • Restart on errors.
Exercise:  UART RX ring
  • Resolution & sampling time.
  • Oversampling & alignment.
  • Timer/HRTIM triggers.
  • DMA continuous/circular.
  • Analog watchdog.
Exercise:  ADC + DMA stream
  • OPAMP PGA modes.
  • COMP thresholds/hysteresis.
  • Routing to timers/EXTI.
  • DAC 12-bit with S&H.
Exercise:  Signal chain
  • CORDIC trig/vectoring.
  • FMAC FIR/IIR blocks.
  • Stream I/O with DMA.
  • Latency vs CPU DSP.
Exercise:  CORDIC vs SW
  • Timer units & outputs.
  • Dead-time & break inputs.
  • Complementary PWM pairs.
  • Sync & ADC trigger points.
  • Fault handling basics.
Exercise:  HRTIM PWM pair
  • PWM → ADC sampling.
  • Scaling & fixed-point tips.
  • Saturation & anti-windup.
  • Simple PI step test.
  • Update rate budgeting.
Exercise:  PI step demo
  • UART 8/9-bit, parity.
  • RX ring + idle detect.
  • SPI CPOL/CPHA, NSS.
  • I²C Fm+ and timeouts.
  • Bus-clear recovery.
Exercise:  Comms trio
  • Classic vs FD basics.
  • Nominal/data bitrates.
  • Filters & message RAM.
  • Loopback/silent modes.
  • Transceiver notes.
Exercise:  FD loopback
  • Sleep/Stop/Standby.
  • Wake sources (EXTI/RTC).
  • LSE vs LSI trade-offs.
  • LPTIM tickless scheme.
  • GPIO leakage states.
Exercise:  Stop + wake
  • Page erase/program.
  • EEPROM emulation.
  • OB: RDP/WRP/BOR.
  • Reset cause logging.
  • Watchdogs IWDG/WWDG.
  • Clocking proven (MCO).
  • I/O safe at boot/sleep.
  • ADC chain documented.
  • Comms error policy.
  • Version/UID/CRC tags.
Exercise:  Self-audit
  • CMSIS-DSP quick tips.
  • Simple FFT sanity.
  • FMAC FIR tuning.
  • HRTIM event logging.
  • ADC calibration pass.
Exercise:  Quick pick: choose one mini-demo and record outcome.
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

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To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

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This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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