STM32L0 Training | Ac6 Training

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STR16STM32L0
This course descirbe the STM32L0 architecture and practical examples

Objectives

  • Understand the Cortex-M0+ core and the STM32L0 SoC.
  • Configure RCC (MSI/HSI16/HSE/LSI/LSE), PLL, and prescalers correctly.
  • Use GPIO/EXTI, timers/LPTIM, DMA, ADC/COMP, and serial buses.
  • Apply ultra-low-power modes and measure consumption.
  • Manage Flash, true Data EEPROM (on L0), Option Bytes, and watchdogs.
  • (If present) bring up USB FS device and TSC capacitive touch.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Practical activities (40-50% of duration)
    • Code examples, exercises and solutions.
    • Remote: one online Linux PC per trainee, with emulated or physical board as needed.
    • Face-to-face / on-site: one PC (one per two beyond six trainees), target board and install manual as needed.
  • Downloadable preconfigured VM to redo the labs afterwards.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by the trainer through the practical exercises, and by quizzes for sections without exercises.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • Core overview
  • Programmer's model
  • Exceptions, NVIC priorities.
  • SysTick, SVC, PendSV basics.
  • Faults on v6-M → HardFault.
  • WFI/WFE sleep entry.
  • SWD; optional SWO/ITM.
Exercise:  Exception Management
  • Lines (L0x1/L0x2/L0x3).
  • Flash / SRAM / PPB map.
  • Peripheral address zones.
  • UID and Flash size regs.
  • Option Bytes overview.
Exercise:  Map & IDs
  • MSI ranges (low-freq steps).
  • HSI16 / HSE basics.
  • PLLs (device-dep.).
  • SYSCLK mux; AHB/APB divs.
  • CCIPR.
  • MCO output; CSS/HSECSS.
Exercise:  Clock profiles
  • Sleep / Low-power run.
  • Low-power sleep / Stop.
  • Standby / VBAT domain.
  • Voltage scaling (Range x).
  • PVD/BOR levels (OB).
  • Fast wake-up notes.
Exercise:  Mode sweep
  • PP/OD, pulls, speeds.
  • AF mapping rules.
  • EXTI lines & priorities.
  • Debounce strategies.
  • Safe I/O at reset.
Exercise:  GPIO & EXTI
  • PWM edge/center.
  • Input capture basics.
  • One-pulse mode.
  • Encoder interface.
  • LPTIM periodic wake.
Exercise:  PWM + capture
  • Channels/requests map.
  • Normal vs circular.
  • HT/TC/TE IRQ flags.
  • Throughput vs latency.
Exercise:  UART RX ring
  • 12-bit ADC basics.
  • Sampling time, ranks.
  • Timer-triggered ADC.
  • DMA continuous/circular.
  • Analog watchdog.
  • COMP to EXTI/timers.
Exercise:  ADC + DMA stream
  • LSE vs LSI trade-offs.
  • Calendar, alarm, wakeup.
  • Backup registers (VBAT).
  • Tickless via RTC/LPTIM.
Exercise:  Tickless blink
  • 8/9-bit, parity/stop.
  • Oversampling 16/8.
  • Blocking / IRQ / DMA.
  • LPUART Stop-mode wake.
  • Error recovery (ORE/FE).
Exercise:  DMA UART
Exercise:  LPUART wake from Stop
  • CPOL/CPHA modes.
  • Data sizes; NSS rules.
  • Full-duplex DMA.
  • Simplex options.
  • Timing check (LA).
Exercise:  SPI loopback DMA
  • Sm/Fm/Fm+ speeds.
  • 7/10-bit addressing.
  • Analog/digital filters.
  • Timeouts; bus-clear.
  • Clock stretching.
  • VBUS sense options.
  • EP/FIFO sizing basics.
  • CDC/DFU quick paths.
  • Clocking constraints.
  • Suspend/resume flow.
Exercise:  CDC echo or DFU
  • Channel groups/IOs.
  • Acquisition timing.
  • Threshold setting.
  • Noise filtering tips.
  • Simple slider/key.
Exercise:  Touch key demo
  • Flash erase/program.
  • True Data EEPROM use.
  • Simple wear leveling.
  • OB: RDP/PCROP/BOR.
  • Read reset cause regs.
  • ROM bootloader ports.
  • DFU/UART/I²C options.
  • Boot pins & OB links.
  • IWDG vs WWDG basics.
  • Reset cause logging.
Exercise:  IWDG + DFU try
  • Clocking proven (MCO).
  • I/O safe at boot/sleep.
  • Low-power numbers noted.
  • Comms error policy set.
  • UID/serial/CRC scheme.
Exercise:  Self-audit
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

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This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

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