STM32 L4/L4+ implementation Training | Ac6 Training

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STR18STM32 L4/L4+ implementation
This course describe the STM32 L4/L4+ architecture and practical examples

Objectives

  • Understand the Cortex-M4F core, DSP/FPU, and the L4/L4+ SoC.
  • Configure RCC (MSI/HSI16/HSE/LSI/LSE) and PLL; validate prescalers.
  • Use GPIO/EXTI, timers/LPTIM/RTC, DMA/DMAMUX, ADC/COMP/OPAMP/DAC.
  • Apply ultra-low-power modes; measure current and wake latency.
  • Bring up USART/SPI/I²C/SAI/DFSDM (where available).
  • Use SDMMC + FatFS, QSPI/OSPI (variant), USB FS device.
  • Manage Flash, Option Bytes, watchdogs, reset causes, and production checklists.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Practical activities (40-50% of duration)
    • Code examples, exercises and solutions.
    • Remote: one online Linux PC per trainee, with emulated or physical board as needed.
    • Face-to-face / on-site: one PC (one per two beyond six trainees), target board and install manual as needed.
  • Downloadable preconfigured VM to redo the labs afterwards.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by the trainer through the practical exercises, and by quizzes for sections without exercises.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • Programmer's Model
  • Exceptions and NVIC priorities.
  • DSP intrinsics (SIMD/MACC).
  • FPU (single-precision).
  • WFI/WFE sleep entry.
  • ITM/SWO printf (if present).
Exercise:  Exception Model
Exercise:  Privilege Mode and Stack
  • AHB/APB buses and bridges.
  • Flash/SRAM/CCM (if any) layout.
  • Peripheral address map.
  • UID & Flash-size registers.
  • Option Bytes snapshot.
Exercise:  Map & IDs
  • MSI ranges and auto-cal.
  • HSI16 / HSE basics.
  • PLLs.
  • SYSCLK mux; AHB/APB divs.
  • CCIPR kernel clocks.
  • MCO output; CSS.
Exercise:  Clock profiles
  • Voltage scaling VOS ranges.
  • Low-power run/sleep.
  • Stop / Standby modes.
  • VBAT/backup domain.
  • PVD/BOR levels.
Exercise:  Mode sweep
  • PP/OD, pulls, speed/drive.
  • AF mapping principles.
  • EXTI lines & priorities.
  • Safe I/O at reset.
Exercise:  EXTI + GPIO
  • PWM edge/center.
  • Input capture, one-pulse.
  • Encoder interface.
  • Master/slave triggers.
  • LPTIM for tickless.
Exercise:  PWM + capture
  • DMA1/DMA2 overview.
  • Requests via DMAMUX.
  • Normal vs circular.
  • HT/TC/TE events.
  • Restart & error paths.
Exercise:  UART RX ring (DMA)
  • Resolution & sampling time.
  • Oversampling & alignment.
  • Timer-triggered regular.
  • Injected group basics.
  • DMA circular streaming.
  • Analog watchdog.
Exercise:  ADC + DMA stream
  • OPAMP PGA modes.
  • COMP thresholds/hysteresis.
  • Routing to timers/EXTI.
  • DAC 12-bit with S&H.
  • Calibrate & verify.
Exercise:  Analog chain
  • USART/LPUART Overview.
  • Oversampling 16/8.
  • Blocking/IRQ/DMA.
  • LPUART Stop-wake.
  • Error handling (ORE/FE).
Exercise:  Robust UART
Exercise:  LPUART wake from stop
  • SPI CPOL/CPHA, NSS.
  • Data sizes & duplex.
  • DMA transfers.
  • I²S basic audio path.
  • SAI TX/RX blocks.
Exercise:  SPI loopback DMA
  • Sm/Fm/Fm+ speeds.
  • 7/10-bit addressing.
  • Analog/digital filters.
  • Timeouts; bus-clear.
  • Clock stretching.
  • LSE vs LSI trade-offs.
  • Calendar, alarm, wakeup.
  • Backup registers.
  • Tickless via RTC/LPTIM.
  • Drift/calibration.
Exercise:  Tickless blink
  • VBUS sense options.
  • EP/FIFO sizing basics.
  • CDC/DFU quick paths.
  • Clocking constraints.
  • Suspend/resume flow.
Exercise:  CDC echo or DFU
  • DFSDM filter paths.
  • Oversampling & decimation.
  • SPI/I²S microphones.
  • DMA to circular buffer.
  • Basic RMS meter.
Exercise:  DFSDM stream
  • SDMMC + FatFS basics.
  • QSPI mapped mode.
  • OSPI (L4+ variants).
  • Buffer align/invalidate.
  • File-I/O sanity tests.
Exercise:  SD + FatFS
  • GPIO leakage strategy.
  • Kernel clocks for LP.
  • Stop entry/exit timing.
  • DMA + LP coexistence.
  • Practical power tips.
Exercise:  Measure Sleep/Stop
  • RNG TRNG.
  • AES/HASH engines.
  • PKA (L4R/L4S).
  • CRC for images/packets.
  • Key storage basics.
Exercise:  CRC/AES
  • Flash erase/program.
  • EEPROM emulation.
  • OB: RDP/PCROP/BOR.
  • Watchdogs IWDG/WWDG.
  • Reset cause logging.
  • ROM bootloader ports.
  • DFU/UART/I²C options.
  • Boot pins & OB ties.
  • Version/UID/CRC tags.
  • Final audit list.
Exercise:  Self-audit
Duration
4 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

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This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

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