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STM32H5

This course describes the STM32H5 architecture

Objectives

  • Grasp STM32H5 fundamentals: Cortex-M33, memory map, dual-bank Flash, clock tree.
  • Build performant drivers with GPDMA (linked-list) and measure impact.
  • Use comms (USART, I²C, SPI), ADC, storage (optional SDMMC/FatFS), and low-power effectively.
  • Introduce security: TrustZone-M, TF-M, and STM32Trust Secure Manager.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Practical activities (40-50% of duration)
    • Code examples, exercises and solutions.
    • Remote: one online Linux PC per trainee, with emulated or physical board as needed.
    • Face-to-face / on-site: one PC (one per two beyond six trainees), target board and install manual as needed.
  • Downloadable preconfigured VM to redo the labs afterwards.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: guided lab work, exercises reviewed with the trainer, end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • Programmer’s model
  • Exceptions/NVIC.
  • SRAM regions; dual-bank Flash overview.
  • MPU basics (no-exec, guards).
Exercise:  Cortex-M33 Exceptions/Interrupts
Exercise:  ARMv8 MPU protection
  • Roles vs CPU; request routing; triggers.
  • Linked-list descriptors; circular vs normal.
  • Cache-safe buffers; invalidate/clean patterns.
Exercise:  ADC → GPDMA ring buffer with LL
  • HSE/HSI/PLL; safe re-clocking.
  • Domain clocks and prescalers.
  • MCO output to verify SYSCLK.
Exercise:  Configure PLL
  • AF mapping; speeds/drive; input filtering.
  • EXTI lines & priorities.
  • Debounce strategies.
  • Board bring-up checklist.
Exercise:  Button EXTI + LED
Exercise:  timestamp ISR latency
  • PWM modes & ARR/CCR.
  • Input capture (period/frequency).
  • One-pulse & basic chaining.
Exercise:  PWM dimmer + frequency meter (IC)
  • Triggers & sampling; oversampling.
  • DMA to ring buffer; window stats.
  • Internal channels (Vref/Temp).
Exercise:  Timer-triggered ADC→GPDMA
  • USART
    • Modes & framing
    • DMA & flow control
    • Errors & diagnostics
  • I²C
    • Master transfers
    • Bus management
    • Robustness
  • SPI
    • Modes & timing
    • DMA & CS
    • Integrity & perf
  • Card detect/init; mount/format.
  • Append patterns; buffering/latency.
  • Wear & safe close on power loss.
  • Run/Sleep/Stop/Standby overview.
  • Wake sources (RTC/EXTI/LPTIM).
  • Regulator notes (SMPS/LDO) & VCORE scaling.
  • Measuring current: setup & pitfalls.
Exercise:  Sleep vs Stop current table; Standby + RTC wake; print reset cause
  • Boot sources; vector relocation.
  • Key OBs; read/verify safely.
  • Dual-bank concepts for updates.
  • RDP/WRP/PCROP overview.
  • Secure vs Non-Secure images; SAU/IDAU; GTZC basics.
  • NSC veneers; minimal secure API design.
  • Peripheral/memory isolation patterns.
  • Enabling/disabling TZ (safe pattern).
Exercise:  Create S + NS projects and secure LED_toggle() veneer
Exercise:  Demonstrate NS access fault → secure wrapper
  • TF-M secure services: RNG, storage, attestation (concepts).
  • STM32Trust Secure Manager: role and enablement path.
  • Placeholders vs production keys; audit trail basics.
  • Rollback/unlock procedures for labs
Exercise:  Dry-run provisioning with placeholders; secure RNG service exposed to NS; restore training state
  • IWDG vs WWDG; service windows.
  • BOR levels; reset-cause logging at boot.
  • ITM/SWO prints; markers around DMA/ISR.
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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