STM32H7 Training | Ac6 Training

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STR11STM32H7
This course descirbe the STM32H7 architecture and practical examples

Objectives

  • Understand STM32H7 (Cortex-M7 @ up to 480 MHz), AXI/TCM memory architecture, caches, and power domains.
  • Configure clocks, Flash/Option Bytes (dual-bank, RDP/WRP/PCROP), and boot flow safely.
  • Drive key peripherals (DMA/MDMA, timers, ADC, comms) with performance in mind.
  • Apply low-power modes across D1/D2/D3 domains; measure impact.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Practical activities (40-50% of duration)
    • Code examples, exercises and solutions.
    • Remote: one online Linux PC per trainee, with emulated or physical board as needed.
    • Face-to-face / on-site: one PC (one per two beyond six trainees), target board and install manual as needed.
  • Downloadable preconfigured VM to redo the labs afterwards.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by the trainer through the practical exercises, and by quizzes for sections without exercises.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • Programmer’s model, exceptions/NVIC, FPU/DP.
  • ITCM/DTCM vs AXI-SRAM: when to place code/data.
  • I-Cache/D-Cache: coherency rules; DMA implications.
  • MPU basics for safety.
Exercise:  Enable caches
Exercise:  Place a hot loop in ITCM
Exercise:  MPU guard
  • AXI matrix overview; masters/targets.
  • DMA vs BDMA vs MDMA roles; scatter-gather, linked lists.
  • Throughput and arbitration basics.
  • Cache maintenance around DMA (invalidate/clean).
Exercise:  ADC→DMA stream with cache-safe buffers; MDMA move/format frames
  • HSE/HSI/PLL1..3; domain clocks (D1/D2/D3).
  • Safe re-clocking; MCO for verification.
  • Timer clocks vs core; prescaler pitfalls.
  • Debug clock freeze effects.
  • Speed, drive, AF mapping; EXTI lines.
  • Debounce strategies; input filtering.
  • Interrupt latency tips on M7.
  • Simple board bring-up checklist.
Exercise:  Button EXTI + LED
  • PWM modes, dead-time (brief), one-pulse.
  • Input capture/measure; trigger chaining.
  • LPTIM vs TIM for low-power.
Exercise:  Timer example
  • Trigger sources; sampling time; oversampling.
  • DMA to ring buffer; window stats in main.
  • Internal channels (Vref, temperature).
Exercise:  Timer-triggered ADC→DMA
  • USART
    • Modes & framing: word length, parity, oversampling; baud tolerance.
    • DMA RX/TX (idle-line, half/full callbacks); ring buffers.
    • Flow control (RTS/CTS) and latency/throughput trade-offs.
  • I²C
    • Master transfers; repeated-START; timing vs bus speed.
    • Clock stretching; timeouts; “bus busy”.
    • Bus recovery for stuck SDA/SCL
  • SPI
    • CPOL/CPHA, word sizes, simplex/half/full-duplex.
    • HW NSS vs GPIO CS; inter-frame delays.
    • DMA streaming; FIFO usage; dummy bytes.
  • Card detect, init/clocking.
  • Mount/format; file append patterns.
  • Buffering/latency; wear; safe close on power loss.
  • Simple log rotation.
Exercise:  Log “timestamp, ADC” to CSV
  • Run/Stop/Standby; what’s retained per domain.
  • Wake sources (RTC/EXTI/LPTIM) across domains.
  • Regulator choices (LDO/SMPS) basics; VCORE scaling.
  • Measurement setup.
Exercise:  Sleep vs Stop current table; Standby + RTC wake; log reset cause.
  • Boot sources (Flash, system memory, SRAM); vector relocation.
  • Key OBs: dual-bank/boot swap (BFB2), WRP/PCROP, RDP levels.
  • Safe read/modify/verify with CubeProgrammer.
  • Bank-swap update concept (overview).
Exercise:  Read OBs; toggle a user OB; verify after reset
  • HardFault decoding; capture LR/PC/CFSR.
  • MPU regioning: stack guards, no-exec, peripheral windows.
  • IWDG vs WWDG; service windows and recovery.
  • BOR levels; reset-cause logging at boot.
  • ITM/SWO quick setup; timestamped printf.
  • Event markers around DMA/ISR.
  • Buffering vs blocking; minimal asserts.
  • Measuring UART vs ITM overhead.
Exercise:  ITM printf + markers; compare overhead to UART
  • FMC vs OCTOSPI use-cases; mapping to AXI.
  • Command, dummy cycles, and memory-mapped mode.
  • Cache/line-fill effects on XIP; prefetch tips.
  • Basic integrity/perf test templates.
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

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This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

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