STM32U5 Training | Ac6 Training

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STR13STM32U5
This course descirbe the STM32U5 architecture

Objectives

  • Understand STM32U5 architecture (Cortex-M33, clocks, resets, memory, peripherals).
  • Configure low-power features and measure real consumption.
  • Implement drivers (GPIO, timers, UART/I²C/SPI, ADC, DMA) with interrupts.
  • Set up secure boot basics and TrustZone-M partitioning (overview + hands-on).
  • Build and debug a small, robust application integrating peripherals, low power, and (optionally) RTOS.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Practical activities (40-50% of duration)
    • Code examples, exercises and solutions.
    • Remote: one online Linux PC per trainee, with emulated or physical board as needed.
    • Face-to-face / on-site: one PC (one per two beyond six trainees), target board and install manual as needed.
  • Downloadable preconfigured VM to redo the labs afterwards.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by the trainer through the practical exercises, and by quizzes for sections without exercises.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • Programmer’s model, stacks, privilege levels.
  • Exceptions & NVIC, SysTick, fault handling (practical tips).
  • Memory protection overview (MPU), TrustZone-M concept (intro).
  • Block diagram, buses, resets.
  • Memory map (Flash, SRAM), caches/buffers (device-specific), option bytes.
  • RCC: clock sources, PLL, prescalers; safe re-clocking patterns.
  • Power pins
  • Pinout
    • Pin Muxing, alternate functions
  • GPIO Module
    • Configuring a GPIO
    • Analog function
    • Integrated pull-up / pull-down
    • I/O pin multiplexer and mapping
    • TrustZone security
Exercise:  Configure EXTI for a button (rising/falling), ISR and debouncing.
  • Roles of DMA vs CPU, request lines, bursts, circular/normal modes
  • LPDMA specifics for ultra-low-power transfers.
  • DMAMUX request mapping and overrun handling.
Exercise:  DMA-GPIO heartbeat
Exercise:  LPDMA ADC stream
Exercise:  DMAMUX remap test
  • Prescalers, ARR, CCR; PWM modes and dead-time basics.
  • Input capture for frequency/period; filtering/glitch removal.
  • One-pulse mode and master/slave timer chaining.
Exercise:  Generate PWM on a timer channel; sweep duty cycle with a button.
Exercise:  Frequency meter using input capture; print measured Hz.
  • LPTIM vs GPTIM, LSE/LSI sources and accuracy.
  • RTC calendar/alarms, sub-second, backup domain care.
  • Wakeup sources and Stop/Standby interplay.
  • Timestamping and drift considerations.
Exercise:  LPTIM periodic wake from Stop
Exercise:  RTC alarm wake + backup register persistence check
  • USART
    • Modes & framing
    • DMA & flow control
    • Errors & diagnostics
  • I²C
    • Master transfers
    • Bus management & recovery
    • Robustness
  • SPI
    • Modes & timing
    • DMA & chip-select
    • Integrity & performance
Exercise:  UART DMA
Exercise:  Periodic sensor
Exercise:  SPI demo
  • Triggers & sampling times; oversampling
  • DMA to ring buffer; window statistics
  • Internal channels (Vref, temperature)
  • Noise sources & layout tips
Exercise:  Timer-triggered ADC + DMA
  • Card detect & init; mount/format
  • File append patterns; buffering
  • Latency & wear considerations
  • Safe close on power loss
Exercise:  Log “timestamp, ADC” to CSV
  • Low-power modes overview
  • Wake sources; retention/autonomous peripherals
  • VOS scaling; SMPS/LDO notes
  • BOR/PVD/PVM supervision
Exercise:  Sleep vs Stop current table
Exercise:  Practical low-power measurements
  • Boot sources & vector relocation
  • Key OBs incl. NS/S boot address
  • RDP overview & implications
  • Read/verify OBs safely
  • SAU/IDAU concepts; NS/S partitioning
  • GTZC: TZSC/TZIC/MPCBB roles
  • Peripheral/memory isolation basics
  • Enabling/disabling TZ
Exercise:  S + NS projects
Exercise:  secure veneer call
Exercise:  demo NS access fault → wrapper
  • Region types & no-exec guards
  • Privileged vs unprivileged access
  • Fault status registers & context capture
  • Fail-safe patterns
Exercise:  MPU fault and logs
  • SAES engine (features overview)
  • OTFDEC for external/XIP content
  • Unique ID & key management basics
  • Watermarks/HDP (high-level)
Exercise:  Secure RNG service from S to NS
  • Debug vs RDP levels
  • Product life-cycle states (brief)
  • Provisioning principles (keys/placeholders)
  • Rollback/unlock procedures
Exercise:  Provisioning dry-run and restore board to training state
  • Bootloader/app split; CRC/hash check
  • “Update pending” flags & rollback
  • Trigger paths (command/flag/comms)
  • Jump sequence & vector table remap
  • IWDG vs WWDG; service windows
  • BOR levels; startup implications
  • Reset flags: POR/WDG/SW/Standby
  • Minimal reset log at boot
Exercise:  Inject hang → IWDG reset; print last reset cause on boot
  • ITM/SWO quick setup
  • Event markers around ISRs/DMA
  • Timestamped printf (lightweight)
  • Buffering vs blocking
Exercise:  ITM printf: visualize DMA callback markers
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

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This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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