STM32F7 Training | Ac6 Training

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STR10STM32F7
This course descirbe the STM32F7 architecture and practical examples

Objectives

  • Grasp the Cortex-M7 core, pipeline, I/D-caches, FPU, SIMD, and MPU.
  • Configure clocks (HSI/HSE/PLL) and prescalers.
  • Use timers (PWM, capture, encoder) and time bases confidently.
  • Build fast, safe DMA paths and handle cache coherency; intro DMA2D.
  • Acquire analog data with ADC + DMA; basics of DAC.
  • Implement USART, SPI/I²S/SAI, I²C with robust error handling.
  • Bring up storage/memory: SDMMC + FatFS, QSPI XIP, FMC SDRAM.
  • Enable connectivity: Ethernet (LwIP ping) and USB OTG FS/HS (CDC).
  • Apply low-power modes; measure wake latency.
  • Set up boot & Option Bytes, watchdogs, and reset-cause logging for production.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Practical activities (40-50% of duration)
    • Code examples, exercises and solutions.
    • Remote: one online Linux PC per trainee, with emulated or physical board as needed.
    • Face-to-face / on-site: one PC (one per two beyond six trainees), target board and install manual as needed.
  • Downloadable preconfigured VM to redo the labs afterwards.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by the trainer through the practical exercises, and by quizzes for sections without exercises.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • Programmer’s model (R0–R15, xPSR)
  • MSP/PSP, exception entry/return
  • Pipeline & branch prediction
  • I-Cache / D-Cache basics
  • ITCM / DTCM usage
  • FPU
  • SIMD
  • MPU regions (intro)
Exercise:  Core & cache sanity
  • AXI matrix, AHB/APB bridges
  • Flash, SRAM1/2/3 layout
  • ITCM/DTCM address zones
  • Peripheral regions (APB1/APB2)
  • QSPI mapped memory (XIP)
  • UID / Flash size registers
  • HSI/HSE/PLL sources
  • PLL M/N/P/Q settings
  • AHB/APB1/APB2 prescalers
  • OverDrive (216 MHz) (variants)
  • Boot pins, Option Bytes
  • Clock security (CSS)
Exercise:  Clock profiles
  • Modes: PP/OD, pulls
  • Speed/drive strength
  • AF mapping rules
  • EXTI lines & priorities
  • Debounce choices
  • Safe I/O at reset
Exercise:  GPIO / EXTI
  • PWM edge/center
  • One-pulse mode
  • Input capture
  • Encoder interface
  • Master/Slave triggers
  • LPTIM (if present)
  • Break/dead-time (adv)
Exercise:  PWM + capture
  • DMA1/DMA2 streams/channels
  • FIFO & burst modes
  • Mem2mem / P2M / M2P
  • Circular/HT/TC/TE IRQs
  • Coherency with D-Cache
  • DMA2D blit (variants)
Exercise:  UART RX DMA ring
  • ADC1..3 (12-bit)
  • Regular vs injected
  • Sampling time, ranks
  • Timer-triggered ADC
  • DMA coupling
  • DAC dual channel
Exercise:  ADC + DMA stream
  • 8/9-bit, parity/stop
  • Oversampling 16/8
  • Blocking / IRQ / DMA
  • RX ring with idle detect
  • Error handling (FE/ORE)
  • Wake from Stop (if used)
Exercise:  Robust UART
  • SPI mode CPOL/CPHA
  • Data sizes, NSS
  • Full-duplex DMA
  • I²S basic audio path
  • SAI blocks (TX/RX)
Exercise:  SPI loopback DMA
  • Sm/Fm/Fm+ speeds
  • Addr 7/10-bit
  • Filters (analog/digital)
  • Timeouts & bus-clear
  • Clock stretching
  • Error recovery
  • SDMMC 1/2
  • FatFS basics
  • QSPI XIP mapping
  • FMC SDRAM/NOR/NAND
  • Cache maintenance (SCB)
  • Buffer alignment rules
Exercise:  SD card + FatFS
  • MII/RMII PHY link
  • Descriptors & rings
  • DMA settings
  • LwIP minimal config
  • Link/ARP/ping tests
Exercise:  Eth bring-up
  • Device/Host roles
  • FS internal / HS via ULPI
  • EP/FIFO sizing
  • CDC/MSC quick paths
  • Low-power suspend/resume
  • I-Cache enable/invalidate
  • D-Cache clean/invalidate
  • Cache pitfalls with DMA
  • ITCM code placement
  • DTCM data placement
  • MPU regions & attrs
Exercise:  TCM vs AXI bench
  • LTDC layers/timings
  • Framebuffer in SDRAM
  • DMA2D color fill/blit
  • DCMI capture basics
  • Simple UI primitives
Exercise:  Color-bar FB
  • Sleep/Stop/Standby
  • OverDrive vs Stop trade-off
  • Wake sources (EXTI/RTC)
  • Clock gating checklist
  • Retention notes
Exercise:  Stop + wake
  • CRC unit
  • RNG TRNG
  • HASH (SHA-1/256)
  • CRYP (AES/TDES)
  • Key storage basics
Exercise:  AES or CRC check
  • Boot ROM interfaces
  • OB: RDP/WRP/BOR
  • Dual-bank (variants)
  • QSPI/SD boot ideas
  • Watchdogs IWDG/WWDG
  • Reset causes log
Exercise:  IWDG + reset log
  • Clocking & wait-states
  • Cache/MPU policy
  • External memory proof
  • Comms robustness list
  • UID/serial/versioning
  • Error counters & logs
Exercise:  Self-audit sheet
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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