STM32L5 Training | Ac6 Training

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STR19STM32L5
This course describes the STM32L5 architecture

Objectives

  • Understand Cortex-M33 + TrustZone-M (secure vs non-secure).
  • Partition memory/peripherals with SAU/IDAU and GTZC.
  • Bring up Secure + Non-Secure projects and veneers (CMSE).
  • Use RCC, GPIO/EXTI, timers/LPTIM, DMA/DMAMUX, ADC/COMP/OPAMP/DAC.
  • Leverage crypto HW (AES/PKA/HASH/RNG) from Secure world.
  • Apply low-power with TZ, RTC/tickless, and safe wake.
  • Set up boot/Option Bytes (TZEN/RDP/PCROP) and basic TF-M / OEMiROT flow.
  • Build a production checklist (watchdogs, reset logs, tamper).
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Practical activities (40-50% of duration)
    • Code examples, exercises and solutions.
    • Remote: one online Linux PC per trainee, with emulated or physical board as needed.
    • Face-to-face / on-site: one PC (one per two beyond six trainees), target board and install manual as needed.
  • Downloadable preconfigured VM to redo the labs afterwards.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by the trainer through the practical exercises, and by quizzes for sections without exercises.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • Core Architecture (STM32 implementation options)
  • Programmer's model
  • Secure vs Non-Secure states.
  • Exception targeting (S/NS).
  • CMSE instructions (veneer).
  • MPU (S/NS regions).
  • FPU (if present).
Exercise:  Exception Management
Exercise:  TrustZone Apps
Exercise:  MPU v8
  • Flash/SRAM/PPB layout.
  • IDAU regions (fixed).
  • SAU adds S/NS windows.
  • UID & Flash-size regs.
  • TZEN Option Byte role.
Exercise:  Map & IDs
  • SAU regions: S, NS, NSC.
  • Veneer table (NSC funcs).
  • Secure gateway calls.
  • Faults on illegal access.
  • Minimal service API design.
Exercise:  NSC “get_random()”
  • MPCBB for SRAM/Flash.
  • TZSC/TZIC periph gates.
  • S/NS interrupt targets.
  • DMA secure vs non-secure.
  • Error flags & reports.
Exercise:  Block NS access
  • CubeIDE dual-image setup.
  • Separate vector tables.
  • Startup order S → NS.
  • Shared headers & ABI.
  • Minimal NS app skeleton.
Exercise:  Dual-image skeleton
  • MSI/HSI16/HSE/PLL.
  • SYSCLK/AHB/APB presc.
  • CCIPR kernel clocks.
  • MCO output, CSS.
  • BOR/PVD quick notes.
Exercise:  Clock profiles + MCO
  • S vs NS GPIO control.
  • EXTI target (S/NS) lines.
  • Debounce choices.
  • SYSCFG & routing notes.
Exercise:  Secure button, NS LED
  • PWM / capture / one-pulse.
  • Encoder basics.
  • Master/slave triggers.
  • LPTIM for tickless wake.
  • Secure timer services.
Exercise:  Secure timebase
  • Channel/request map.
  • Circular vs normal.
  • HT/TC/TE handling.
  • Coherency & barriers.
  • Secure DMA policy.
Exercise:  NS UART RX ring
  • Resolution & sampling.
  • Oversampling option.
  • Timer-triggered regular.
  • DMA circular streaming.
  • Watchdog & thresholds.
Exercise:  ADC + DMA (NS)
  • UART 8/9-bit, parity.
  • RX ring + idle detect.
  • SPI CPOL/CPHA & DMA.
  • I²C timeouts, bus-clear.
  • S/NS peripheral policy.
Exercise:  Comms (NS)
  • AES engine modes.
  • HASH (SHA-1/256).
  • PKA (ECC ops).
  • RNG TRNG source.
  • Key/nonce handling.
Exercise:  Secure AES service
  • ROM boot flow (L5).
  • OEMiROT / SBSFU / TF-M.
  • Image signing basics.
  • NV counters / rollback.
  • Logs & update hooks.
Exercise:  Signed blink (demo)
  • Sleep/Stop/Standby.
  • Secure wake sources.
  • SRAM/Reg retention.
  • Re-init SAU on wake.
  • Policy: who sleeps.
Exercise:  Stop + secure wake
  • LSE vs LSI trade-offs.
  • Calendar/alarm/wakeup.
  • Backup registers.
  • Tickless via LPTIM/RTC.
Exercise:  Tickless blink (NS)
  • VBUS sense options.
  • EP/FIFO sizing.
  • CDC/DFU quick path.
  • Clock constraints.
  • Suspend/resume.
  • QSPI mapped reads.
  • SDMMC + FatFS.
  • Cache/ALIGN notes.
  • Secure vs NS access.
  • Basic file I/O test.
Exercise:  SD + FatFS (NS)
  • TZEN/RDP/PCROP/WRP.
  • BOR/PVD levels.
  • Tamper (TAMP) basics.
  • Watchdogs IWDG/WWDG.
  • Reset cause logging.
Exercise:  OB snapshot & IWDG
  • Partition doc (SAU/GTZC).
  • Keys & secure services.
  • Boot/update steps.
  • Low-power numbers.
  • UID/serial/CRC tags.
Exercise:  Self-audit sheet
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

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To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

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This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

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