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STR91X implementation

This course covers STR9 ARM-based MCU family

Objectives

  • The course details the hardware implementation of the STR91x microcontrollers.
  • The boot sequence and the clocking are explained.
  • The course focuses on the low level programming of the ARM966 CPU.
  • Practical labs on integrated peripherals are based on I/O functions provided by ST.

  • Note that ACSYS does not sell emulation probes and IDEs. Consequently this course has not been designed to convince attendees to buy a particular IDE. The unique objective consists in providing sufficient knowledge to attendees so that they can successfully design a system based on STR9.

  • This course has been delivered several times to companies developing embedded systems, such as industrial equipments.
A lot of programming examples have been developed by ACSYS to explain the boot sequence, the vector table and the operation of embedded peripherals.
•  They have been developed with 2 different IDEs : Keil and IAR.
•  Consequently for on site course, it is up to the customer to select the IDE under which labs will be run.
A more detailed course description is available on request at training@ac6-training.com
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • ARM core based architecture
  • Features of AHB and APB buses
  • The main three blocks : platform, core and input / output peripherals
  • Operating modes : user, system, super, IRQ, FIQ, undef and abort
  • Pipeline, calculation of the CPI
  • Branch cache
  • Clarifying the data path
  • Tightly Coupled Memories
  • ARM vs Thumb instruction sets, interworking
  • Stack management
  • Benefits of condition set capability in ARM state
  • C-to-Assembly interface
  • Exception mechanism, handler table
  • Debug facilities
  • AHB/APB Bridges, split transactions, error handling
  • Internal 96 KB SRAM,
  • Flash memory
  • Program and erase sequences
  • VIC Interrupt controller
  • Wake-up / interrupt unit
  • System timers : Real Time Clock, Watchdog timer
  • Low voltage detectors
  • Clocking
  • Reset causes
  • Start-up sequence, fetch of the first instruction
  • Low power modes
  • External Memory Interface
  • I/O Ports
  • Timers
    • Output compare and input capture capabilities, force compare modes
    • One pulse mode
    • Output PWM mode, on-the-fly modification of the duty cycle
    • Input PWM mode, pulse measurement
  • DMA controller
    • Request priority management between the 16 channels
    • Scatter / gather operation, transfer descriptor chaining
    • Error management
  • Analog-to-Digital Converter
    • One-shot or continuous conversion
    • Analog watchdog with interrupt generation
  • 3-phase induction motor controller
    • Tacho counter operating modes
    • Rotor speed measurement
    • Dead time generator
  • I2C interface
    • I2C protocol basics
    • Slave mode vs master mode
    • Support for DMA
  • Synchronous Serial Peripheral [SSP]
    • SPI protocol basics
    • Queue mode operation
    • Transfer sequence
  • UART
    • Queue operation mode
    • Hardware flow control
    • IrDA mode
    • Support for DMA
  • CAN controller
    • CAN protocol basics
    • CAN controller organization
    • Message objects
    • Filtering of received messages
    • FIFO mode management
  • USB slave interface
    • USB protocol basics
    • Buffer description block, buffer descriptor table
    • DMA controller used to move data between buffers and EndPoints
    • Endpoint initialization
  • Fast Ethernet controller
    • 802.3 MAC basics
    • Connection to the PHY : MII bus
    • Management interface, auto-negotiation
    • DMA controller operation
    • Frame filtering
    • VLAN support
    • Error management
Duration
4 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 7 July 2026

Booking one of our trainings is subject to our General Terms of Sales

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