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SPEAr 1310 implementation

This course covers the software and hardware implementation of ST Spear 1310 high-end SoC

Objectives

  • The course details the hardware implementation of the SPEAr1310 SoC.
  • The course focuses on the boot sequence, the clocking and the power management strategies.
  • The course explains all parameters that affect the performance of the system in order to easily perform the final tuning.
  • The interfaces to high speed bus, such as PCIe, SATA and Ethernet are covered in depth.
  • An overview of the Cortex-A9MP core helps to understand issues caused by MMU, cache and snooping.
  • Interrupt management through ARM GIC is explained through a lab.
  • The course also covers the hardware implementation, particularly the DDR3 and NAND flash controllers.

  • Products and services offered by ACSYS:
    • ACSYS is able to assist the customer by providing consultancies. Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
Labs included in this course are compiled with RVDS 4.1 and executed under Lauterbach Trace32.
A more detailed course description is available on request at training@ac6-training.com
This document is necessary to tailor the course to specific customer needs and to define the exact schedule.

  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • ARM core based architecture
  • On-chip memories
  • Clarifying the internal data paths: AXI interconnect, NOC, peripheral buses
  • Organization of a board based on SPEAr1310
  • Memory mapping
  • Presentation of the core, architecture and programming model
  • MMU and TLBs
  • Level 1 caches
  • Cache coherency
  • Level 2 cache
  • Timers and watchdogs
  • Parity protection
  • PCM
    • Generation of supply switch control signals for power islands
    • Generation of shutoff commands for external DDR 1V2 and 1V5/1V8 supply lines
    • Monitoring of voltage detector outputs for each power island
    • Selecting wake-up sources
  • Clock Manager
    • Clock sources
    • Integrated PLLs
    • Clock generators
  • System Reset Controller
    • System boot mode selection
    • Hardware initialization phase
    • Startup sequence
  • IOMUX module
  • General Purpose Input interrupt request capability
  • Keyboard controller
  • Integrated semaphores
  • Temperature sensor
  • Cortex-A9MP and PL310 L2 cache IP instantiation options
  • Integrated interrupt controller (GIC), detail of interrupt mapping
  • Implementing hardware coherency between IO masters and cluster through ACP
  • Multi-layer interconnect matrix, crossbars and shared link
  • Connectivity matrix
  • Introduction to CoreSight, DAP features
  • Program Trace Macrocell
  • Cross Triggering Interfaces
  • Timers
    • 4x General-Purpose Timer and High Resolution Timer
    • Real Time Clock
  • DMA controllers
    • DMA multiplexer
    • Multi-block transfers achieved through linked lists
    • Programmable channel priority
    • 16 handshaking interfaces for source and destination peripherals
  • Analog-to-Digital converter
    • 10-bit resolution
    • 8 analog input channels
    • DMA hardware handshaking interface
  • Serial Management Interface
  • SATA II
    • Controlling the state of the 3 SATA ports
    • Initialization of the controller
    • AHCI software host Interface
    • Hardware-assisted native command queuing for up to 32 entries
    • Integrated DMA channels
  • Memory Card Interface (MCIF)
    • SD, MMC and SDIO protocols support
    • Compact Flash/CF+ Host controller
  • Multi-Port DDR Controller
    • Introduction to DDR2 and DDR3, write-leveling, ZQ calibration
    • Pinout, clocking
    • DDR calibration and delay-lines
    • Advanced bank look-ahead features for high memory throughput
    • Setting DDR-device specific timing parameters
    • Reporting errors
  • Flexible Static Memory Controller
    • External device address mapping
    • Interfaces with static memory-mapped devices including NOR flash, SRAM, Cellular SRAM and CosmoRAM
    • NAND flash controller with hardware ECC
    • External asynchronous wait control
  • PCI controller
    • 32-bit / 66-MHz operation
    • Programmable for acting as host or device
  • PCI Express controller
    • Muxing SATA and PCIe onto high-speed lanes
    • Configuration as Agent or Root Complex
    • Interrupt management
    • Hot plug support
    • Error management
  • Synchronous Serial Port
  • I2C interfaces
  • UART
  • USB
    • Integrated USB2.0 PHYs
    • Explaining what is OTG, SRP and HNP
    • High-speed operation
    • EHCI support, muxing periodic and non-periodic traffics
    • Full speed operation, OHCI
  • Gigabit Ethernet Controller
    • PHY connection
    • Incoming frame filtering mechanisms, hash tables
    • VLAN support
    • TCP-IP offload
    • Audio video (AV) feature, transmitting time-sensitive informations
    • IEEE1588 protocol support, timestamp registers
    • Media Information Base
  • CAN controller
    • CAN protocol basics
    • message objects
  • One Time Programming interfaces
  • Security Coprocessor C3
    • Multipurpose, instruction driven, programmable DMA-based co-processor
    • Sequence to encrypt / decrypt data
    • Sequence to generate / check a SHA signature
Duration
5 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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